#define MAX_DOZE_WAITING_TIMES_9x 64
-#define RadioB_ArrayLength RadioB_ArrayLengthPciE
#define MACPHY_Array_PGLength MACPHY_Array_PGLengthPciE
#define PHY_REG_1T2RArrayLength PHY_REG_1T2RArrayLengthPciE
extern u32 Rtl8192PciEPHY_REG_1T2RArray[PHY_REG_1T2RArrayLengthPciE];
#define RTL8192E_RADIO_A_ARR_LEN 246
extern u32 Rtl8192PciERadioA_Array[RTL8192E_RADIO_A_ARR_LEN];
-#define RadioB_ArrayLengthPciE 78
-extern u32 Rtl8192PciERadioB_Array[RadioB_ArrayLengthPciE];
+#define RTL8192E_RADIO_B_ARR_LEN 78
+extern u32 Rtl8192PciERadioB_Array[RTL8192E_RADIO_B_ARR_LEN];
#define RTL8192E_MACPHY_ARR_LEN 18
extern u32 Rtl8192PciEMACPHY_Array[RTL8192E_MACPHY_ARR_LEN];
#define MACPHY_Array_PGLengthPciE 30