ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
                };
        };
+
+       mcu_cpsw: ethernet@46000000 {
+               compatible = "ti,j721e-cpsw-nuss";
+               #address-cells = <2>;
+               #size-cells = <2>;
+               reg = <0x0 0x46000000 0x0 0x200000>;
+               reg-names = "cpsw_nuss";
+               ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
+               dma-coherent;
+               clocks = <&k3_clks 18 22>;
+               clock-names = "fck";
+               power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>;
+
+               dmas = <&mcu_udmap 0xf000>,
+                      <&mcu_udmap 0xf001>,
+                      <&mcu_udmap 0xf002>,
+                      <&mcu_udmap 0xf003>,
+                      <&mcu_udmap 0xf004>,
+                      <&mcu_udmap 0xf005>,
+                      <&mcu_udmap 0xf006>,
+                      <&mcu_udmap 0xf007>,
+                      <&mcu_udmap 0x7000>;
+               dma-names = "tx0", "tx1", "tx2", "tx3",
+                           "tx4", "tx5", "tx6", "tx7",
+                           "rx";
+
+               ethernet-ports {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       cpsw_port1: port@1 {
+                               reg = <1>;
+                               ti,mac-only;
+                               label = "port1";
+                               ti,syscon-efuse = <&mcu_conf 0x200>;
+                               phys = <&phy_gmii_sel 1>;
+                       };
+               };
+
+               davinci_mdio: mdio@f00 {
+                       compatible = "ti,cpsw-mdio","ti,davinci_mdio";
+                       reg = <0x0 0xf00 0x0 0x100>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       clocks = <&k3_clks 18 22>;
+                       clock-names = "fck";
+                       bus_freq = <1000000>;
+               };
+       };
 };