* "last user address" is set even if bootp is used without parameters
(and it uses default address).
+======================================================================
+Modifications for 0.9.0:
+======================================================================
+
+* Added support for LWMON board
+
+* Added support for GTH board
+ (Thomas Lange, 19 Mar 2001)
+
+* Misc patches:
+ - Latest Hymod code
+ - minor patch for the "immap" command
+ - minor patch to the "ctrlc" stuff to support interrupting during
+ interpreting a command line with multiple sections separated by
+ semi-colons. i.e. if any command is interrupted with control-C,
+ this fact is recorded and the command line parser will not
+ continue running further commands.
+ - backport to the 8xx platform of the new i2c driver that was
+ introduced for the 8260 platform
+ (Patch by Murray Jensen, 05 Mar 2001)
+
+* Fixes for PCMCIA code
+ (Patch by Thomas Lange, 19 Mar 2001)
+
+* Misc ADCIOP modifications
+ (Patch by Stefan Roese, 16 Mar 2001)
+
+* Fix sector erase bug on Walnut board
+ (Patch by Raymond Lo, 14 Mar 2001)
+
+* Added BeOS and *BSD #defines to several files
+ (Patch by Erik Theisen, 14 Mar 2001)
+
+* MBX8xx Board fixes:
+ - problem with basic clocking due to bad calculation of the PLPRCR
+ register's multiplication factor
+ - couldn't access the board's NVRAM due to incorrect initialization
+ order of chip selects; the Boot ROM's CS0 was overiding the setup
+ of the NVRAM.
+ - initialization of BR and OR memory controller registers was not
+ compliant with the MBX860 Users Manual
+ - board level configuration and status register # 2's mapping was
+ defined in the wrong bit order. This was resulting in a incorrect
+ error message about NVRAM battery failure.
+ - Re-enabled CFG_CMD_ENV to allow access to the NVRAM
+ (Patch by Erik Theisen, 14 Mar 2001)
+
+* Network driver fixes
+ (Patch by Anne-Sophie Harnois, 13 Mar 2001)
+
+* board_pre_init() patch for CANBT/CPCI405/AR405/CANBT/WALNUT405/CPCIISER4
+ (Patch from Stefan Roese, 12 Mar 2001)
+
+* Fix problems booting PPCBoot on MBX860
+ (Patch from Paul Ruhland, 10 Mar 2001)
+
+* Fixed bug in command parsing code
+ (Patch from Dave Ellis, 05 Mar 2001)
+
======================================================================
Modifications for 0.8.3:
======================================================================
N: Wolfgang Denk
E: wd@denx.de
-D: PPCBOOT initial version
+D: PPCBOOT initial version, continuing maintenance
W: www.denx.de
N: Dan A. Dickey
E: Murray.Jensen@cmst.csiro.au
D: Added port to the Cogent platform
+N: Thomas Lange
+E: thomas@corelatus.com
+D: Support for GTH board; lots of PCMCIA fixes
+
N: Dan Malek
E: dan@netx4.com
D: FADSROM, the grandfather of all of this
E: robt@flyingpig.com
D: Port to MBX860T and Sandpoint8240
+N: Erik Theisen
+E: etheisen@mindspring.com
+D: MBX8xx patches
+
N: Christian Vejlbo
E: christian.vejlbo@tellabs.com
D: FADS860T ethernet support
[ -d LOG ] || mkdir LOG || exit 1
-LIST=" \
- TQM823L TQM850L TQM855L TQM860L FPS850L SM850 \
- ETX094 SPD823TS IVMS8 IVML24 \
- FADS823 FADS850SAR FADS860T MBX \
- CPCI405 ADCIOP AR405 CANBT \
+LIST=""
+
+#########################################################################
+## MPC8xx Systems
+#########################################################################
+
+LIST="$LIST \
+ TQM823L TQM850L FPS850L TQM855L TQM860L SM850 \
+ ETX094 SPD823TS IVMS8 IVML24 \
+ hermes IP860 lwmon \
+ ESTEEM192E \
+ SXNI855T \
+ FADS823 FADS850SAR FADS860T ADS860 \
+ cogent_mpc8xx \
+ GENIETV \
+ MBX MBX860T \
+ RPXlite \
+ GTH \
+"
+
+#########################################################################
+## PPC4xx Systems
+#########################################################################
+
+LIST="$LIST \
+ CPCI405 CPCIISER4 \
WALNUT405 \
- cogent_mpc8xx \
- GENIETV \
- SXNI855T \
- cogent_mpc8260 hymod \
- sbc8260 \
+ AR405 CANBT ADCIOP \
+"
+
+#########################################################################
+## MPC8240 Systems
+#########################################################################
+
+LIST="$LIST \
Sandpoint8240 \
- hermes IP860 \
+"
+
+#########################################################################
+## MPC8260 Systems
+#########################################################################
+
+LIST="$LIST \
+ hymod \
+ cogent_mpc8260 \
rsdproto \
- RPXlite \
- ESTEEM192E \
- CPCIISER4 \
+ sbc8260 \
"
[ $# = 0 ] && set $LIST
unconfig:
rm -f include/config.h include/config.mk
+#########################################################################
+## MPC8xx Systems
+#########################################################################
+
TQM823L_config \
TQM850L_config \
FPS850L_config \
echo "CPU = mpc8xx" >>config.mk ; \
echo "#include <config_$(@:_config=).h>" >config.h
+SM850_config : unconfig
+ @echo "Configuring for $(@:_config=) Board..." ; \
+ cd include ; \
+ echo "ARCH = ppc" > config.mk ; \
+ echo "BOARD = tqm8xx" >>config.mk ; \
+ echo "CPU = mpc8xx" >>config.mk ; \
+ echo "#include <config_$(@:_config=).h>" >config.h
+
ETX094_config : unconfig
@echo "Configuring for $(@:_config=) Board..." ; \
cd include ; \
echo "CPU = mpc8xx" >>config.mk ; \
echo "#include <config_$(@:_config=).h>" >config.h
-SM850_config : unconfig
+hermes_config : unconfig
@echo "Configuring for $(@:_config=) Board..." ; \
cd include ; \
echo "ARCH = ppc" > config.mk ; \
- echo "BOARD = tqm8xx" >>config.mk ; \
+ echo "BOARD = hermes" >>config.mk ; \
echo "CPU = mpc8xx" >>config.mk ; \
echo "#include <config_$(@:_config=).h>" >config.h
-hermes_config : unconfig
+IP860_config : unconfig
@echo "Configuring for $(@:_config=) Board..." ; \
cd include ; \
echo "ARCH = ppc" > config.mk ; \
- echo "BOARD = hermes" >>config.mk ; \
+ echo "BOARD = ip860" >>config.mk ; \
echo "CPU = mpc8xx" >>config.mk ; \
echo "#include <config_$(@:_config=).h>" >config.h
-IP860_config : unconfig
+lwmon_config: unconfig
@echo "Configuring for $(@:_config=) Board..." ; \
cd include ; \
echo "ARCH = ppc" > config.mk ; \
- echo "BOARD = ip860" >>config.mk ; \
+ echo "BOARD = lwmon" >>config.mk ; \
+ echo "CPU = mpc8xx" >>config.mk ; \
+ echo "#include <config_$(@:_config=).h>" >config.h
+
+ESTEEM192E_config: unconfig
+ @echo "Configuring for $(@:_config=) Board..." ; \
+ cd include ; \
+ echo "ARCH = ppc" > config.mk ; \
+ echo "BOARD = esteem192e" >>config.mk ; \
echo "CPU = mpc8xx" >>config.mk ; \
echo "#include <config_$(@:_config=).h>" >config.h
echo "CPU = mpc8xx" >>config.mk ; \
echo "#include <config_$(@:_config=).h>" >config.h
-CPCI405_config: unconfig
+cogent_mpc8xx_config: unconfig
@echo "Configuring for $(@:_config=) Board..." ; \
cd include ; \
echo "ARCH = ppc" > config.mk ; \
- echo "BOARD = cpci405" >>config.mk ; \
- echo "CPU = ppc4xx" >>config.mk ; \
+ echo "BOARD = cogent" >>config.mk ; \
+ echo "CPU = mpc8xx" >>config.mk ; \
echo "#include <config_$(@:_config=).h>" >config.h
-CPCIISER4_config: unconfig
+GENIETV_config: unconfig
@echo "Configuring for $(@:_config=) Board..." ; \
cd include ; \
echo "ARCH = ppc" > config.mk ; \
- echo "BOARD = cpciiser4" >>config.mk ; \
- echo "CPU = ppc4xx" >>config.mk ; \
+ echo "BOARD = genietv" >>config.mk ; \
+ echo "CPU = mpc8xx" >>config.mk ; \
echo "#include <config_$(@:_config=).h>" >config.h
-WALNUT405_config:unconfig
+MBX_config: unconfig
@echo "Configuring for $(@:_config=) Board..." ; \
cd include ; \
echo "ARCH = ppc" > config.mk ; \
- echo "BOARD = walnut405">>config.mk ; \
- echo "CPU = ppc4xx" >>config.mk ; \
+ echo "BOARD = mbx8xx" >>config.mk ; \
+ echo "CPU = mpc8xx" >>config.mk ; \
echo "#include <config_$(@:_config=).h>" >config.h
-AR405_config: unconfig
+MBX860T_config: unconfig
@echo "Configuring for $(@:_config=) Board..." ; \
cd include ; \
echo "ARCH = ppc" > config.mk ; \
- echo "BOARD = ar405" >>config.mk ; \
- echo "CPU = ppc4xx" >>config.mk ; \
+ echo "BOARD = mbx" >>config.mk ; \
+ echo "CPU = mpc8xx" >>config.mk ; \
echo "#include <config_$(@:_config=).h>" >config.h
-CANBT_config: unconfig
+RPXlite_config: unconfig
@echo "Configuring for $(@:_config=) Board..." ; \
cd include ; \
echo "ARCH = ppc" > config.mk ; \
- echo "BOARD = canbt" >>config.mk ; \
+ echo "BOARD = RPXlite" >>config.mk ; \
+ echo "CPU = mpc8xx" >>config.mk ; \
+ echo "#include <config_$(@:_config=).h>" >config.h
+
+#########################################################################
+## PPC4xx Systems
+#########################################################################
+
+CPCI405_config: unconfig
+ @echo "Configuring for $(@:_config=) Board..." ; \
+ cd include ; \
+ echo "ARCH = ppc" > config.mk ; \
+ echo "BOARD = cpci405" >>config.mk ; \
echo "CPU = ppc4xx" >>config.mk ; \
echo "#include <config_$(@:_config=).h>" >config.h
-ADCIOP_config: unconfig
+CPCIISER4_config: unconfig
@echo "Configuring for $(@:_config=) Board..." ; \
cd include ; \
echo "ARCH = ppc" > config.mk ; \
- echo "BOARD = adciop" >>config.mk ; \
+ echo "BOARD = cpciiser4" >>config.mk ; \
echo "CPU = ppc4xx" >>config.mk ; \
echo "#include <config_$(@:_config=).h>" >config.h
-cogent_mpc8xx_config: unconfig
+WALNUT405_config:unconfig
@echo "Configuring for $(@:_config=) Board..." ; \
cd include ; \
echo "ARCH = ppc" > config.mk ; \
- echo "BOARD = cogent" >>config.mk ; \
- echo "CPU = mpc8xx" >>config.mk ; \
+ echo "BOARD = walnut405">>config.mk ; \
+ echo "CPU = ppc4xx" >>config.mk ; \
echo "#include <config_$(@:_config=).h>" >config.h
-GENIETV_config: unconfig
+AR405_config: unconfig
@echo "Configuring for $(@:_config=) Board..." ; \
cd include ; \
echo "ARCH = ppc" > config.mk ; \
- echo "BOARD = genietv" >>config.mk ; \
- echo "CPU = mpc8xx" >>config.mk ; \
+ echo "BOARD = ar405" >>config.mk ; \
+ echo "CPU = ppc4xx" >>config.mk ; \
echo "#include <config_$(@:_config=).h>" >config.h
-MBX_config: unconfig
+CANBT_config: unconfig
@echo "Configuring for $(@:_config=) Board..." ; \
cd include ; \
echo "ARCH = ppc" > config.mk ; \
- echo "BOARD = mbx8xx" >>config.mk ; \
- echo "CPU = mpc8xx" >>config.mk ; \
+ echo "BOARD = canbt" >>config.mk ; \
+ echo "CPU = ppc4xx" >>config.mk ; \
echo "#include <config_$(@:_config=).h>" >config.h
-MBX860T_config: unconfig
+ADCIOP_config: unconfig
@echo "Configuring for $(@:_config=) Board..." ; \
cd include ; \
echo "ARCH = ppc" > config.mk ; \
- echo "BOARD = mbx" >>config.mk ; \
- echo "CPU = mpc8xx" >>config.mk ; \
+ echo "BOARD = adciop" >>config.mk ; \
+ echo "CPU = ppc4xx" >>config.mk ; \
echo "#include <config_$(@:_config=).h>" >config.h
+#########################################################################
+## MPC8240 Systems
+#########################################################################
+
Sandpoint8240_config: unconfig
@echo "Configuring for $(@:_config=) Board..." ; \
cd include ; \
echo "CPU = mpc8240" >>config.mk ; \
echo "#include <config_$(@:_config=).h>" >config.h
+#########################################################################
+## MPC8260 Systems
+#########################################################################
+
hymod_config: unconfig
@echo "Configuring for $(@:_config=) Board..." ; \
cd include ; \
echo "CPU = mpc8260" >>config.mk ; \
echo "#include <config_$(@:_config=).h>" >config.h
-RPXlite_config: unconfig
- @echo "Configuring for $(@:_config=) Board..." ; \
- cd include ; \
- echo "ARCH = ppc" > config.mk ; \
- echo "BOARD = RPXlite" >>config.mk ; \
- echo "CPU = mpc8xx" >>config.mk ; \
- echo "#include <config_$(@:_config=).h>" >config.h
-
-ESTEEM192E_config: unconfig
+sbc8260_config: unconfig
@echo "Configuring for $(@:_config=) Board..." ; \
cd include ; \
echo "ARCH = ppc" > config.mk ; \
- echo "BOARD = esteem192e" >>config.mk ; \
- echo "CPU = mpc8xx" >>config.mk ; \
+ echo "BOARD = sbc8260" >>config.mk ; \
+ echo "CPU = mpc8260" >>config.mk ; \
echo "#include <config_$(@:_config=).h>" >config.h
-sbc8260_config: unconfig
+GTH_config: unconfig
@echo "Configuring for $(@:_config=) Board..." ; \
cd include ; \
echo "ARCH = ppc" > config.mk ; \
- echo "BOARD = sbc8260" >>config.mk ; \
- echo "CPU = mpc8260" >>config.mk ; \
+ echo "BOARD = gth" >>config.mk ; \
+ echo "CPU = mpc8xx" >>config.mk ; \
echo "#include <config_$(@:_config=).h>" >config.h
#########################################################################
load and run it dynamically.
+Where to get help:
+==================
+
+In case you have questions about, problems with or contributions for
+PPCBoot you should send a message to the PPCBoot mailing list at
+<ppcboot-users@lists.sourceforge.net>. There is also an archive of
+previous traffic on the mailing list - please search the archive
+before asking FAQ's. Please see
+http://lists.sourceforge.net/lists/listinfo/ppcboot-users/
+
+
Where we come from:
===================
/* ------------------------------------------------------------------------- */
+int board_pre_init (void)
+{
+ /*
+ * Set port pin in escc2 to keep living
+ */
+ *(unsigned char *)0x2000033e = 0xf7; /* ESCC2: PCR */
+ *(unsigned char *)0x2000033c = 0x08; /* ESCC2: PVR */
+
+ return 0;
+}
+
+
/*
* Check Board Identity:
- *
- * Test TQ ID string (TQM8xx...)
- * If present, check for "L" type (no second DRAM bank),
- * otherwise "L" type is assumed as default.
- *
- * Return 1 for "L" type, 0 else.
*/
int checkboard (void)
--- /dev/null
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS = $(BOARD).o flash.o
+
+$(LIB): .depend $(OBJS)
+ $(AR) crv $@ $^
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+ifeq ($(CONFIG_START_IN_RAM),1)
+TEXT_BASE = 0
+else
+TEXT_BASE = 0x080000000
+endif
+OBJCFLAGS = --set-section-flags=.ppcenv=contents,alloc,load,data
+
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppcboot.h>
+#include <mpc8xx.h>
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+/*-----------------------------------------------------------------------
+ * Protection Flags:
+ */
+#define FLAG_PROTECT_SET 0x01
+#define FLAG_PROTECT_CLEAR 0x02
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile memctl8xx_t *memctl = &immap->im_memctl;
+ unsigned long size_b0, size_b1;
+ int i;
+
+ //printf("faking");
+
+ return(0x4fffff);
+
+ /* Init: no FLASHes known */
+ for (i=0; i < CFG_MAX_FLASH_BANKS; ++i)
+ {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ }
+
+ /* Static FLASH Bank configuration here - FIXME XXX */
+
+ size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+ if (flash_info[0].flash_id == FLASH_UNKNOWN)
+ {
+ printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",size_b0, size_b0<<20);
+ }
+
+#if 0
+ if (FLASH_BASE1_PRELIM != 0x0) {
+ size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]);
+
+ if (size_b1 > size_b0) {
+ printf ("## ERROR: Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n",size_b1, size_b1<<20,size_b0, size_b0<<20);
+
+ flash_info[0].flash_id = FLASH_UNKNOWN;
+ flash_info[1].flash_id = FLASH_UNKNOWN;
+ flash_info[0].sector_count = -1;
+ flash_info[1].sector_count = -1;
+ flash_info[0].size = 0;
+ flash_info[1].size = 0;
+ return (0);
+ }
+ } else {
+#endif
+ size_b1 = 0;
+// }
+
+ /* Remap FLASH according to real size */
+ memctl->memc_or0 = CFG_OR0_PRELIM;
+ memctl->memc_br0 = CFG_BR0_PRELIM;
+
+ /* Re-do sizing to get full correct info */
+ size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+
+ flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+
+ /* monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET, CFG_FLASH_BASE,CFG_FLASH_BASE+CFG_MONITOR_LEN-1, &flash_info[0]);
+
+ if (size_b1)
+ {
+ //memctl->memc_or1 = CFG_OR1_PRELIM;
+ //memctl->memc_br1 = CFG_BR1_PRELIM;
+
+ /* Re-do sizing to get full correct info */
+ size_b1 = flash_get_size((vu_long *)(CFG_FLASH_BASE + size_b0), &flash_info[1]);
+
+ flash_get_offsets (CFG_FLASH_BASE + size_b0, &flash_info[1]);
+
+ /* monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET, CFG_FLASH_BASE, CFG_FLASH_BASE+CFG_MONITOR_LEN-1, &flash_info[1]);
+ }
+ else
+ {
+// memctl->memc_or1 = CFG_OR1_PRELIM;
+// FIXME memctl->memc_br1 = CFG_BR1_PRELIM;
+
+ flash_info[1].flash_id = FLASH_UNKNOWN;
+ flash_info[1].sector_count = -1;
+ }
+
+ flash_info[0].size = size_b0;
+ flash_info[1].size = size_b1;
+
+ return (size_b0 + size_b1);
+}
+
+
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+ int i;
+
+ /* set up sector start adress table */
+ if (info->flash_id & FLASH_BTYPE)
+ {
+ /* set sector offsets for bottom boot block type */
+ for (i = 0; i < info->sector_count; i++)
+ {
+ info->start[i] = base + (i * 0x00040000);
+ }
+ }
+ else
+ {
+ /* set sector offsets for top boot block type */
+ i = info->sector_count - 1;
+ for (; i >= 0; i--)
+ {
+ info->start[i] = base + i * 0x00040000;
+ }
+ }
+
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t *info)
+{
+ int i;
+
+ if (info->flash_id == FLASH_UNKNOWN)
+ {
+ printf ("missing or unknown FLASH type\n");
+ return;
+ }
+
+ switch (info->flash_id & FLASH_VENDMASK)
+ {
+ case FLASH_MAN_AMD: printf ("AMD "); break;
+ case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
+ default: printf ("Unknown Vendor "); break;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK)
+ {
+
+#if 0
+ case FLASH_AM040B: printf ("AM29F040B (4 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM040T: printf ("AM29F040T (4 Mbit, top boot sect)\n");
+ break;
+#endif
+ case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+ break;
+ default: printf ("Unknown Chip Type\n");
+ break;
+ }
+
+ printf (" Size: %ld MB in %d Sectors\n",info->size >> 20, info->sector_count);
+
+ printf (" Sector Start Addresses:");
+
+ for (i=0; i<info->sector_count; ++i)
+ {
+ if ((i % 5) == 0)
+ {
+ printf ("\n ");
+ }
+
+ printf (" %08lX%s", info->start[i],info->protect[i] ? " (RO)" : " " );
+ }
+
+ printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+ short i;
+#if 0
+ ulong base = (ulong)addr;
+#endif
+ uchar value;
+
+ /* Write auto select command: read Manufacturer ID */
+#if 0
+ addr[0x0555] = 0x00AA00AA;
+ addr[0x02AA] = 0x00550055;
+ addr[0x0555] = 0x00900090;
+#else
+ addr[0x0555] = 0xAAAAAAAA;
+ addr[0x02AA] = 0x55555555;
+ addr[0x0555] = 0x90909090;
+#endif
+
+ value = addr[0];
+
+ switch (value)
+ {
+ case AMD_MANUFACT:case 0x01:
+ info->flash_id = FLASH_MAN_AMD;
+ break;
+
+ case FUJ_MANUFACT:
+ info->flash_id = FLASH_MAN_FUJ;
+ break;
+
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ break;
+ }
+
+ value = addr[1]; /* device ID */
+
+ switch (value)
+ {
+#if 0
+ case AMD_ID_F040B:
+ info->flash_id += FLASH_AM040B;
+ info->sector_count = 8;
+ info->size = 0x00200000;
+ break; /* => 2 MB */
+#endif
+ case AMD_ID_LV400T:
+ info->flash_id += FLASH_AM400T;
+ info->sector_count = 11;
+ info->size = 0x00100000;
+ break; /* => 1 MB */
+
+ case AMD_ID_LV400B:
+ info->flash_id += FLASH_AM400B;
+ info->sector_count = 11;
+ info->size = 0x00100000;
+ break; /* => 1 MB */
+
+ case AMD_ID_LV800T:
+ info->flash_id += FLASH_AM800T;
+ info->sector_count = 19;
+ info->size = 0x00200000;
+ break; /* => 2 MB */
+
+ case AMD_ID_LV800B:
+ info->flash_id += FLASH_AM800B;
+ info->sector_count = 19;
+ info->size = 0x00200000;
+ break; /* => 2 MB */
+
+ case AMD_ID_LV160T:
+ info->flash_id += FLASH_AM160T;
+ info->sector_count = 35;
+ info->size = 0x00400000;
+ break; /* => 4 MB */
+
+ case AMD_ID_LV160B:
+ info->flash_id += FLASH_AM160B;
+ info->sector_count = 35;
+ info->size = 0x00400000;
+ break; /* => 4 MB */
+#if 0 /* enable when device IDs are available */
+ case AMD_ID_LV320T:
+ info->flash_id += FLASH_AM320T;
+ info->sector_count = 67;
+ info->size = 0x00800000;
+ break; /* => 8 MB */
+
+ case AMD_ID_LV320B:
+ info->flash_id += FLASH_AM320B;
+ info->sector_count = 67;
+ info->size = 0x00800000;
+ break; /* => 8 MB */
+#endif
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ return (0); /* => no or unknown flash */
+
+ }
+
+#if 0
+ /* set up sector start adress table */
+ if (info->flash_id & FLASH_BTYPE) {
+ /* set sector offsets for bottom boot block type */
+ info->start[0] = base + 0x00000000;
+ info->start[1] = base + 0x00008000;
+ info->start[2] = base + 0x0000C000;
+ info->start[3] = base + 0x00010000;
+ for (i = 4; i < info->sector_count; i++) {
+ info->start[i] = base + (i * 0x00020000) - 0x00060000;
+ }
+ } else {
+ /* set sector offsets for top boot block type */
+ i = info->sector_count - 1;
+ info->start[i--] = base + info->size - 0x00008000;
+ info->start[i--] = base + info->size - 0x0000C000;
+ info->start[i--] = base + info->size - 0x00010000;
+ for (; i >= 0; i--) {
+ info->start[i] = base + i * 0x00020000;
+ }
+ }
+#else
+ flash_get_offsets ((ulong)addr, &flash_info[0]);
+#endif
+
+ /* check for protected sectors */
+ for (i = 0; i < info->sector_count; i++)
+ {
+ /* read sector protection at sector address, (A7 .. A0) = 0x02 */
+ /* D0 = 1 if protected */
+ addr = (volatile unsigned long *)(info->start[i]);
+ info->protect[i] = addr[2] & 1;
+ }
+
+ /*
+ * Prevent writes to uninitialized FLASH.
+ */
+ if (info->flash_id != FLASH_UNKNOWN)
+ {
+ addr = (volatile unsigned long *)info->start[0];
+#if 0
+ *addr = 0x00F000F0; /* reset bank */
+#else
+ *addr = 0xF0F0F0F0; /* reset bank */
+#endif
+ }
+
+ return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+void flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+ vu_long *addr = (vu_long*)(info->start[0]);
+ int flag, prot, sect, l_sect;
+ ulong start, now, last;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("- missing\n");
+ } else {
+ printf ("- no sectors to erase\n");
+ }
+ return;
+ }
+
+ if ((info->flash_id == FLASH_UNKNOWN) ||
+ (info->flash_id > FLASH_AMD_COMP)) {
+ printf ("Can't erase unknown flash type - aborted\n");
+ return;
+ }
+
+ prot = 0;
+ for (sect=s_first; sect<=s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+
+ if (prot) {
+ printf ("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ } else {
+ printf ("\n");
+ }
+
+ l_sect = -1;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+#if 0
+ addr[0x0555] = 0x00AA00AA;
+ addr[0x02AA] = 0x00550055;
+ addr[0x0555] = 0x00800080;
+ addr[0x0555] = 0x00AA00AA;
+ addr[0x02AA] = 0x00550055;
+#else
+ addr[0x0555] = 0xAAAAAAAA;
+ addr[0x02AA] = 0x55555555;
+ addr[0x0555] = 0x80808080;
+ addr[0x0555] = 0xAAAAAAAA;
+ addr[0x02AA] = 0x55555555;
+#endif
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect<=s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ addr = (vu_long*)(info->start[sect]);
+#if 0
+ addr[0] = 0x00300030;
+#else
+ addr[0] = 0x30303030;
+#endif
+ l_sect = sect;
+ }
+ }
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* wait at least 80us - let's wait 1 ms */
+ udelay (1000);
+
+ /*
+ * We wait for the last triggered sector
+ */
+ if (l_sect < 0)
+ goto DONE;
+
+ start = get_timer (0);
+ last = start;
+ addr = (vu_long*)(info->start[l_sect]);
+#if 0
+ while ((addr[0] & 0x00800080) != 0x00800080)
+#else
+ while ((addr[0] & 0xFFFFFFFF) != 0xFFFFFFFF)
+#endif
+ {
+ if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+ printf ("Timeout\n");
+ return;
+ }
+ /* show that we're waiting */
+ if ((now - last) > 1000) { /* every second */
+ putc ('.');
+ last = now;
+ }
+ }
+
+DONE:
+ /* reset to read mode */
+ addr = (volatile unsigned long *)info->start[0];
+#if 0
+ addr[0] = 0x00F000F0; /* reset bank */
+#else
+ addr[0] = 0xF0F0F0F0; /* reset bank */
+#endif
+
+ printf (" done\n");
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+ ulong cp, wp, data;
+ int i, l, rc;
+
+ wp = (addr & ~3); /* get lower word aligned address */
+
+ /*
+ * handle unaligned start bytes
+ */
+ if ((l = addr - wp) != 0) {
+ data = 0;
+ for (i=0, cp=wp; i<l; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+ for (; i<4 && cnt>0; ++i) {
+ data = (data << 8) | *src++;
+ --cnt;
+ ++cp;
+ }
+ for (; cnt==0 && i<4; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+
+ if ((rc = write_word(info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += 4;
+ }
+
+ /*
+ * handle word aligned part
+ */
+ while (cnt >= 4) {
+ data = 0;
+ for (i=0; i<4; ++i) {
+ data = (data << 8) | *src++;
+ }
+ if ((rc = write_word(info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += 4;
+ cnt -= 4;
+ }
+
+ if (cnt == 0) {
+ return (0);
+ }
+
+ /*
+ * handle unaligned tail bytes
+ */
+ data = 0;
+ for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+ data = (data << 8) | *src++;
+ --cnt;
+ }
+ for (; i<4; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+
+ return (write_word(info, wp, data));
+}
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+ vu_long *addr = (vu_long*)(info->start[0]);
+ ulong start;
+ int flag;
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*((vu_long *)dest) & data) != data) {
+ return (2);
+ }
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+#if 0
+ addr[0x0555] = 0x00AA00AA;
+ addr[0x02AA] = 0x00550055;
+ addr[0x0555] = 0x00A000A0;
+#else
+ addr[0x0555] = 0xAAAAAAAA;
+ addr[0x02AA] = 0x55555555;
+ addr[0x0555] = 0xA0A0A0A0;
+#endif
+
+ *((vu_long *)dest) = data;
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* data polling for D7 */
+ start = get_timer (0);
+#if 0
+ while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080))
+#else
+ while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080))
+#endif
+ {
+ if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+ return (1);
+ }
+ }
+ return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Adapted from FADS and other board config files to GTH by thomas@corelatus.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppcboot.h>
+#include <config.h>
+#include "mpc8xx.h"
+
+#ifdef CONFIG_BDM
+#undef printf
+#define printf(a,...) /* nothing */
+#endif
+
+
+int checkboard (void){
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ int Id=0;
+ int Rev=0;
+ u32 Pbdat;
+ // Turn on leds and setup for reading rev and id
+
+#define PB_OUTS (PB_BLUE_LED|PB_ID_GND)
+#define PB_INS (PB_ID_0|PB_ID_1|PB_ID_2|PB_ID_3|PB_REV_1|PB_REV_0)
+
+ immap->im_cpm.cp_pbpar &= ~(PB_OUTS|PB_INS);
+
+ immap->im_cpm.cp_pbdir &= ~PB_INS;
+
+ immap->im_cpm.cp_pbdir |= PB_OUTS;
+ immap->im_cpm.cp_pbodr |= PB_OUTS;
+ immap->im_cpm.cp_pbdat &= ~PB_OUTS;
+
+ // Turn on front led to show that we are alive
+ immap->im_ioport.iop_papar &= ~PA_FRONT_LED;
+ immap->im_ioport.iop_padir |= PA_FRONT_LED;
+ immap->im_ioport.iop_paodr |= PA_FRONT_LED;
+ immap->im_ioport.iop_padat &= ~PA_FRONT_LED;
+
+ Pbdat = immap->im_cpm.cp_pbdat;
+
+ if(!(Pbdat&PB_ID_0)) Id+=1;
+ if(!(Pbdat&PB_ID_1)) Id+=2;
+ if(!(Pbdat&PB_ID_2)) Id+=4;
+ if(!(Pbdat&PB_ID_3)) Id+=8;
+
+ if(Pbdat&PB_REV_0) Rev +=1;
+ if(Pbdat&PB_REV_1) Rev +=2;
+
+ // Turn ID off since we dont need it anymore
+ immap->im_cpm.cp_pbdat |= PB_ID_GND;
+
+ printf("GTH board, rev %d, id=0x%01x\n",Rev,Id);
+ return 0;
+}
+
+#define _NOT_USED_ 0xffffffff
+const uint sdram_table[] = {
+ // Single read, offset 0
+ 0x0f3dfc04, 0x0eefbc04, 0x01bf7c04, 0x0feafc00,
+ 0x1fb5fc45, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+ // Burst read, Offset 0x8, 4 reads,
+ 0x0f3dfc04, 0x0eefbc04, 0x00bf7c04, 0x00ffec00,
+ 0x00fffc00, 0x01eafc00, 0x1fb5fc00, 0xfffffc45,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+ // Not used part of burst read is used for MRS, Offset 0x14
+ 0xefeabc34, 0x1fb57c34, 0xfffffc05, _NOT_USED_,
+ // _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+ // Single write, Offset 0x18
+ 0x0f3dfc04, 0x0eebbc00, 0x01a27c04, 0x1fb5fc45,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+ // Burst write, Offset 0x20. 4 writes
+ 0x0f3dfc04, 0x0eebbc00, 0x00b77c00, 0x00fffc00,
+ 0x00fffc00, 0x01eafc04, 0x1fb5fc45, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+ // Not used part of burst write is used for precharge, Offset 0x2C
+ 0x0ff5fc04, 0xfffffc05, _NOT_USED_, _NOT_USED_,
+ // _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+ // Period timer service. Offset 0x30. Refresh. Wait at least 70 ns after refresh command
+ 0x1ffd7c04, 0xfffffc04, 0xfffffc04, 0xfffffc05,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+ // Exception, Offset 0x3C
+ 0xfffffc04, 0xfffffc05, _NOT_USED_, _NOT_USED_ };
+
+const uint fpga_table[] = {
+ // Single read, offset 0
+ 0x0cffec04, 0x00ffec04, 0x00ffec04, 0x00ffec04,
+ 0x00fffc04, 0x00fffc00, 0x00ffec04, 0xffffec05,
+
+ // Burst read, Offset 0x8
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+ // Single write, Offset 0x18
+ 0x0cffec04, 0x00ffec04, 0x00ffec04, 0x00ffec04,
+ 0x00fffc04, 0x00fffc00, 0x00ffec04, 0xffffec05,
+
+ // Burst write, Offset 0x20.
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+ // Period timer service. Offset 0x30.
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+ // Exception, Offset 0x3C
+ 0xfffffc04, 0xfffffc05, _NOT_USED_, _NOT_USED_ };
+
+int _initsdram(uint base, uint noMbytes){
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile memctl8xx_t *mc = &immap->im_memctl;
+
+ mc->memc_mptpr = MPTPR_PTP_DIV16; // (16-17)
+
+ ///// Setup SDRAM in UPMA /////
+
+ // GPL_0 is connected instead of A19 to SDRAM.
+ // According to table 16-17, AMx should be 001, i.e. type 1
+ // and GPL_0 should hold address A10 when multiplexing
+
+ mc->memc_mamr = (0x2E<<MAMR_PTA_SHIFT)|MAMR_PTAE|MAMR_AMA_TYPE_1|MAMR_G0CLA_A10|
+ MAMR_RLFA_1X|MAMR_WLFA_1X|MAMR_TLFA_1X; // (16-13)
+
+ upmconfig(UPMA, (uint *)sdram_table,sizeof(sdram_table)/sizeof(uint));
+
+ // Perform init of sdram ( Datasheet Page 9 )
+ // Precharge
+ mc->memc_mcr = 0x8000212C; // run upm a at 0x2C (16-15)
+
+ // Run 2 refresh cycles
+ mc->memc_mcr = 0x80002130; // run upm a at 0x30 (16-15)
+ mc->memc_mcr = 0x80002130; // run upm a at 0x30 (16-15)
+
+ // Set Mode register
+ mc->memc_mar = 0x00000088; // set mode register (address) to 0x022 (16-17) Lower 2 bits are not connected to chip
+ mc->memc_mcr = 0x80002114; // run upm a at 0x14 (16-15)
+
+ //FIXME when not 32MB
+ // CS1, base 0x0000000 - 32 Mbyte, use UPM A
+
+ mc->memc_or1 = 0xfe000000|OR_CSNT_SAM;
+ mc->memc_br1 = BR_MS_UPMA|BR_V; // SDRAM base always 0
+
+ ///// Setup FPGA in UPMB /////
+ upmconfig(UPMB, (uint *)fpga_table,sizeof(fpga_table)/sizeof(uint));
+
+ // Enable UPWAITB
+ mc->memc_mbmr = MAMR_GPL_B4DIS; // (16-13)
+
+ // CS2, base FPGA_2_BASE - 4 MByte, use UPM B 32 Bit
+ mc->memc_or2 = 0xffc00000| OR_BI;
+ mc->memc_br2 = FPGA_2_BASE|BR_MS_UPMB|BR_V;
+
+ // CS3, base FPGA_3_BASE - 4 MByte, use UPM B 16 bit
+ mc->memc_or3 = 0xffc00000|OR_BI;
+ mc->memc_br3 = FPGA_3_BASE|BR_MS_UPMB|BR_V|BR_PS_16;
+
+ return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+void _sdramdisable(void)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+ memctl->memc_br1 = 0x00000000;
+
+ /* maybe we should turn off upmb here or something */
+}
+
+/* ------------------------------------------------------------------------- */
+
+int initsdram(uint base, uint *noMbytes)
+{
+ uint m;
+
+ *noMbytes = 32;
+
+#ifdef CONFIG_START_IN_RAM
+ // SDRAM is already setup. Dont touch it
+ return 0;
+#else
+
+ if(!_initsdram(base, m))
+ {
+
+ return 0;
+ }
+ else
+ {
+ _sdramdisable();
+
+ return -1;
+ }
+#endif
+}
+
+long int initdram (int board_type)
+{
+ u32 *i;
+ u32 j;
+ u32 k;
+ // GTH only have SDRAM
+ uint sdramsz;
+
+ if (!initsdram(0x00000000, &sdramsz)) {
+ printf("(%u MB SDRAM) ", sdramsz);
+ }
+ else{
+ /********************************
+ *SDRAM ERROR, HALT PROCESSOR
+ *********************************/
+ printf("SDRAM ERROR\n");
+ while(1);
+ }
+
+#ifndef CONFIG_START_IN_RAM
+
+#define U32_S ((sdramsz<<18)-1)
+
+#if 1
+ // Do a simple memory test
+ for(i=(u32*)0,j=0;(u32)i<U32_S;i+=2,j+=2){
+ *i = j+(j<<17);
+ *(i+1) = ~(j+(j<<18));
+ }
+
+ printf(".");
+
+ for(i=(u32*)0,j=0;(u32)i<U32_S;i+=2,j+=2){
+ k = *i;
+ if(k != (j+(j<<17))){
+ printf("Mem test error, i=0x%x, 0x%x\n, 0x%x",(u32)i,j,k);
+ while(1);
+ }
+ k = *(i+1);
+ if(k != ~(j+(j<<18))){
+ printf("Mem test error(+1), i=0x%x, 0x%x\n, 0x%x",(u32)i+1,j,k);
+ while(1);
+ }
+ }
+#endif
+
+ // Clear memory
+ for(i=(u32*)0;(u32)i<U32_S;i++){
+ *i = 0;
+ }
+#endif // !start in ram
+
+ return (sdramsz << 20);
+}
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ *(.text)
+ common/environment.o(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x0FFF) & 0xFFFFF000;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(4096);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(4096);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
+
LIB = lib$(BOARD).a
-OBJS = $(BOARD).o flash.o
+OBJS = $(BOARD).o flash.o cmd_fpga.o
$(LIB): .depend $(OBJS)
$(AR) crv $@ $^
#include <command.h>
#include <net.h>
#include <asm/iopin_8260.h>
-#include <asm/hymod.h>
-#include <hymod/cmd_fpga.h>
+#include <board/hymod/cmd_fpga.h>
#define LOAD_SUCCESS 0
#define LOAD_FAIL_NOCONF 1
TEXT_BASE = 0x40000000
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)
OBJCFLAGS = --set-section-flags=.ppcenv=contents,alloc,load,data
#include <ppcboot.h>
#include <mpc8260.h>
-#include <hymod/flash.h>
+#include <board/hymod/flash.h>
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
#include <ppcboot.h>
#include <mpc8260.h>
#include <ioports.h>
+#include <i2c.h>
+#include <asm/iopin_8260.h>
/* ------------------------------------------------------------------------- */
/* PA9 */ { 1, 0, 0, 0, 0, 0 }, /* FLASH STS0 */
/* PA8 */ { 1, 0, 0, 0, 0, 0 }, /* FLASH ~PE */
/* PA7 */ { 1, 0, 0, 0, 0, 0 }, /* WATCH ~HRESET */
- /* PA6 */ { 1, 0, 0, 0, 0, 0 }, /* VC DONE */
- /* PA5 */ { 1, 0, 0, 0, 0, 0 }, /* VC INIT */
- /* PA4 */ { 1, 0, 0, 0, 0, 0 }, /* VC ~PROG */
- /* PA3 */ { 1, 0, 0, 0, 0, 0 }, /* VM ENABLE */
- /* PA2 */ { 1, 0, 0, 0, 0, 0 }, /* VM DONE */
- /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* VM INIT */
- /* PA0 */ { 1, 0, 0, 0, 0, 0 } /* VM ~PROG */
+ /* PA6 */ { 1, 0, 0, 0, 1, 0 }, /* VC DONE */
+ /* PA5 */ { 1, 0, 0, 1, 1, 0 }, /* VC INIT */
+ /* PA4 */ { 1, 0, 0, 1, 0, 0 }, /* VC ~PROG */
+ /* PA3 */ { 1, 0, 0, 1, 0, 0 }, /* VM ENABLE */
+ /* PA2 */ { 1, 0, 0, 0, 1, 0 }, /* VM DONE */
+ /* PA1 */ { 1, 0, 0, 1, 1, 0 }, /* VM INIT */
+ /* PA0 */ { 1, 0, 0, 1, 0, 0 } /* VM ~PROG */
},
/* Port B configuration */
/* ------------------------------------------------------------------------- */
+/*
+ * AMI FS6377 Clock Generator configuration table
+ *
+ * the table indexes 0 - 15 correspond to FS6377 registers 0 - 15. the
+ * data is written to the FS6377 via the i2c bus - hence the addr var.
+ */
+
+uchar fs6377_addr = 0x5c;
+
+uchar fs6377_regs[16] = {
+ 12, 75, 64, 25, 144, 128, 24, 75,
+ 224, 18, 75, 192, 224, 16, 16, 248
+};
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * special board initialisation, after clocks and timebase have been
+ * set up but before environment and serial are initialised.
+ *
+ * added so that very early initialisations can be done using the i2c
+ * driver (which requires the clocks, to calculate the dividers, and
+ * the timebase, for udelay())
+ */
+
+void
+board_postclk_init(void)
+{
+ i2c_state_t state;
+
+ i2c_init(50000, 0xfe); /* slave address not important */
+
+ i2c_newio(&state);
+
+ /*
+ * the secondary address is the register number from where to
+ * start the write - I want to write all the registers
+ *
+ * don't bother checking return status - we have no console yet
+ * to print it on, nor any RAM to store it in - it will be obvious
+ * if this doesn't work
+ */
+ (void) i2c_send(&state, fs6377_addr, 0,
+ I2CF_ENABLE_SECONDARY|I2CF_START_COND|I2CF_STOP_COND,
+ sizeof (fs6377_regs), fs6377_regs);
+
+ (void) i2c_doio(&state);
+}
+
+/* ------------------------------------------------------------------------- */
+
/*
* Check Board Identity: Hardwired to HYMOD
*/
/* ------------------------------------------------------------------------- */
+/*
+ * miscellaneous (early - while running in flash) initialisations.
+ */
+
+#define _NOT_USED_ 0xFFFFFFFF
+
+uint upmb_table[] = {
+ /* Read Single Beat (RSS) - offset 0x00 */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ /* Read Burst (RBS) - offset 0x08 */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ /* Write Single Beat (WSS) - offset 0x18 */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ /* Write Burst (WSS) - offset 0x20 */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ /* Refresh Timer (PTS) - offset 0x30 */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ /* Exception Condition (EXS) - offset 0x3c */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_
+};
+
+uint upmc_table[] = {
+ /* Read Single Beat (RSS) - offset 0x00 */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ /* Read Burst (RBS) - offset 0x08 */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ /* Write Single Beat (WSS) - offset 0x18 */
+ 0xF0E00000, 0xF0A00000, 0x00A00000, 0x30A00000,
+ 0xF0F40007, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ /* Write Burst (WSS) - offset 0x20 */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ /* Refresh Timer (PTS) - offset 0x30 */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ /* Exception Condition (EXS) - offset 0x3c */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_
+};
+
+int
+misc_init_f(void)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile memctl8260_t *memctl = &immap->im_memctl;
+
+ printf (" FPGA: ");
+
+ upmconfig(UPMB, upmb_table, sizeof upmb_table / sizeof upmb_table[0]);
+ memctl->memc_mbmr = CFG_MBMR;
+
+ upmconfig(UPMC, upmc_table, sizeof upmc_table / sizeof upmc_table[0]);
+ memctl->memc_mcmr = CFG_MCMR;
+
+ printf ("configured\n");
+ return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
long
initdram(int board_type)
{
return (CFG_SDRAM_SIZE << 20);
}
+
+#ifndef CFG_HYMOD_NO_EEPROMS
+static int
+check_prom(hymod_prom_t *pp)
+{
+ hymod_prom_t copy = *pp;
+
+ copy.crc = 0;
+ return (crc32(0, (uchar *)©, sizeof copy) != pp->crc);
+}
+#endif
+
+/* ------------------------------------------------------------------------- */
+/* read the i2c serial eeprom (Philips PCF8594C-2) on the hymod main board, */
+/* and also on the mezzanine board, if it is plugged in */
+/* the PCF8594C-2 has 2 x 256 byte pages, with the bottom bit of the 7 bit */
+/* i2c address selecting the page, but since we need less than 256 bytes */
+/* we are always going to use page 0 */
+
+uchar main_addr = 0x50;
+uchar mezz_addr = 0x52;
+
+void
+misc_init_r(bd_t *bd)
+{
+ hymod_conf_t *cp = &bd->bi_hymod_conf;
+#ifndef CFG_HYMOD_NO_EEPROMS
+ i2c_state_t state;
+ uchar prom_addr = 0;
+ ulong crc;
+ int rc;
+#endif
+
+ memset((void *)cp, 0, sizeof (*cp));
+
+ /*
+ * attempt to read the prom on both the main board and the
+ * mezzanine board
+ */
+
+ puts(" EEPROM:main...");
+
+#ifdef CFG_HYMOD_NO_EEPROMS
+
+ puts("(faked)");
+
+ /* XXX get these from environment variables */
+
+ cp->main_prom.date.year = 2001;
+ cp->main_prom.date.month = 2;
+ cp->main_prom.date.day = 8;
+ cp->main_prom.serno = 1;
+ cp->main_prom.type = HYMOD_BDTYPE_IO;
+ cp->main_prom.rev = 1;
+ cp->main_prom.ver = 1;
+ cp->main_prom.nfpga = 1;
+ cp->main_prom.ftype[0] = HYMOD_FPGATYPE_XCV300E;
+ cp->main_prom.crc = \
+ crc32(0, (uchar *)&cp->main_prom, sizeof (hymod_prom_t));
+
+#else
+
+ i2c_init(100000, 0xfe); /* slave address not important */
+
+ i2c_newio(&state);
+
+ /* send the prom address to read from - always zero */
+ rc = i2c_send(&state, main_addr, 0, I2CF_START_COND, 1, &prom_addr);
+ if (rc != 0) {
+ printf("BAD (send rc=%d)", rc);
+ goto main_fail;
+ }
+
+ /* receive all the prom data bytes in one go */
+ rc = i2c_receive(&state, main_addr, 0, I2CF_START_COND|I2CF_STOP_COND,
+ sizeof (hymod_prom_t), (uchar *)&cp->main_prom);
+ if (rc != 0) {
+ printf("BAD (recv rc=%d)", rc);
+ goto main_fail;
+ }
+
+ rc = i2c_doio(&state);
+ if (rc != 0) {
+ printf("BAD (doio rc=%d)", rc);
+ memset((void *)&cp->main_prom, 0, sizeof (hymod_prom_t));
+ goto main_fail;
+ }
+
+ if (check_prom(&cp->main_prom)) {
+ printf("BAD (crc %08lx!=%08lx)", crc, cp->main_prom.crc);
+ memset((void *)&cp->main_prom, 0, sizeof (hymod_prom_t));
+ goto main_fail;
+ }
+
+ puts("OK");
+
+#endif
+
+ cp->main_mmap[0].prog.exists = 1;
+ cp->main_mmap[0].prog.size = FPGA_MAIN_CFG_SIZE;
+ cp->main_mmap[0].prog.base = FPGA_MAIN_CFG_BASE;
+
+ cp->main_mmap[0].reg.exists = 1;
+ cp->main_mmap[0].reg.size = FPGA_MAIN_REG_SIZE;
+ cp->main_mmap[0].reg.base = FPGA_MAIN_REG_BASE;
+
+ cp->main_mmap[0].port.exists = 1;
+ cp->main_mmap[0].port.size = FPGA_MAIN_PORT_SIZE;
+ cp->main_mmap[0].port.base = FPGA_MAIN_PORT_BASE;
+
+ cp->main_iopins[0].prog_pin.port = FPGA_MAIN_PROG_PORT;
+ cp->main_iopins[0].prog_pin.pin = FPGA_MAIN_PROG_PIN;
+ cp->main_iopins[0].prog_pin.flag = 1;
+ cp->main_iopins[0].init_pin.port = FPGA_MAIN_INIT_PORT;
+ cp->main_iopins[0].init_pin.pin = FPGA_MAIN_INIT_PIN;
+ cp->main_iopins[0].init_pin.flag = 1;
+ cp->main_iopins[0].done_pin.port = FPGA_MAIN_DONE_PORT;
+ cp->main_iopins[0].done_pin.pin = FPGA_MAIN_DONE_PIN;
+ cp->main_iopins[0].done_pin.flag = 1;
+#ifdef FPGA_MAIN_ENABLE_PORT
+ cp->main_iopins[0].enable_pin.port = FPGA_MAIN_ENABLE_PORT;
+ cp->main_iopins[0].enable_pin.pin = FPGA_MAIN_ENABLE_PIN;
+ cp->main_iopins[0].enable_pin.flag = 1;
+#endif
+
+ cp->flags |= HYMOD_FLAG_MAINVALID;
+
+#ifndef CFG_HYMOD_NO_EEPROMS
+
+main_fail:
+
+#endif
+
+ puts(", mezz...");
+
+#ifdef CFG_HYMOD_NO_EEPROMS
+
+ puts("(faked)");
+
+ /* XXX get these from environment variables */
+
+ cp->mezz_prom.date.year = 2001;
+ cp->mezz_prom.date.month = 2;
+ cp->mezz_prom.date.day = 8;
+ cp->mezz_prom.serno = 1;
+ cp->mezz_prom.type = HYMOD_BDTYPE_DISPLAY;
+ cp->mezz_prom.rev = 1;
+ cp->mezz_prom.ver = 1;
+ cp->mezz_prom.nfpga = 1;
+ cp->mezz_prom.ftype[0] = HYMOD_FPGATYPE_XCV300E;
+ cp->mezz_prom.crc = \
+ crc32(0, (uchar *)&cp->mezz_prom, sizeof (hymod_prom_t));
+
+#else
+
+ i2c_newio(&state);
+
+ /* send the prom address to read from - always zero */
+ rc = i2c_send(&state, mezz_addr, 0, I2CF_START_COND, 1, &prom_addr);
+ if (rc != 0) {
+ printf("BAD (send rc=%d)", rc);
+ goto mezz_fail;
+ }
+
+ /* receive all the prom data bytes in one go */
+ rc = i2c_receive(&state, mezz_addr, 0, I2CF_START_COND|I2CF_STOP_COND,
+ sizeof (hymod_prom_t), (uchar *)&cp->mezz_prom);
+ if (rc != 0) {
+ printf("BAD (recv rc=%d)", rc);
+ goto mezz_fail;
+ }
+
+ rc = i2c_doio(&state);
+ if (rc != 0) {
+ printf("BAD (doio rc=%d - mezz card not present?)", rc);
+ memset((void *)&cp->mezz_prom, 0, sizeof (hymod_prom_t));
+ goto mezz_fail;
+ }
+
+ if (check_prom(&cp->mezz_prom)) {
+ printf("BAD (crc %08lx!=%08lx)", crc, cp->mezz_prom.crc);
+ memset((void *)&cp->mezz_prom, 0, sizeof (hymod_prom_t));
+ goto mezz_fail;
+ }
+
+ puts("OK");
+
+#endif
+
+ cp->mezz_mmap[0].prog.exists = 1;
+ cp->mezz_mmap[0].prog.size = FPGA_MEZZ_CFG_SIZE;
+ cp->mezz_mmap[0].prog.base = FPGA_MEZZ_CFG_BASE;
+
+ cp->mezz_mmap[0].reg.exists = 0;
+
+ cp->mezz_mmap[0].port.exists = 0;
+
+ cp->mezz_iopins[0].prog_pin.port = FPGA_MEZZ_PROG_PORT;
+ cp->mezz_iopins[0].prog_pin.pin = FPGA_MEZZ_PROG_PIN;
+ cp->mezz_iopins[0].prog_pin.flag = 1;
+ cp->mezz_iopins[0].init_pin.port = FPGA_MEZZ_INIT_PORT;
+ cp->mezz_iopins[0].init_pin.pin = FPGA_MEZZ_INIT_PIN;
+ cp->mezz_iopins[0].init_pin.flag = 1;
+ cp->mezz_iopins[0].done_pin.port = FPGA_MEZZ_DONE_PORT;
+ cp->mezz_iopins[0].done_pin.pin = FPGA_MEZZ_DONE_PIN;
+ cp->mezz_iopins[0].done_pin.flag = 1;
+#ifdef FPGA_MEZZ_ENABLE_PORT
+ cp->mezz_iopins[0].enable_pin.port = FPGA_MEZZ_ENABLE_PORT;
+ cp->mezz_iopins[0].enable_pin.pin = FPGA_MEZZ_ENABLE_PIN;
+ cp->mezz_iopins[0].enable_pin.flag = 1;
+#endif
+
+ cp->flags |= HYMOD_FLAG_MEZZVALID;
+
+#ifndef CFG_HYMOD_NO_EEPROMS
+
+mezz_fail:
+
+#endif
+
+ puts("\n");
+}
/* wait at least 80us - let's wait 1 ms */
udelay (1000);
- while (((status = *addr) & 0x0080) == 0) {
+ while (((status = *addr) & 0x0080) != 0x0080) {
if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
*addr = 0x00FF; /* reset to read mode */
start = get_timer (0);
- while (((status = *addr) & 0x0080) == 0) {
+ while (((status = *addr) & 0x0080) != 0x0080) {
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
*addr = 0x00FF; /* restore read mode */
return (1);
--- /dev/null
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS = $(BOARD).o flash.o
+
+$(LIB): .depend $(OBJS)
+ $(AR) crv $@ $^
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Ulrich Lutz, Speech Design GmbH, ulutz@datalab.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# LWE Monitorcontroller Litronic LCD IV boards
+#
+
+TEXT_BASE = 0x40000000
--- /dev/null
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppcboot.h>
+#include <mpc8xx.h>
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+# ifndef CFG_ENV_ADDR
+# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET)
+# endif
+# ifndef CFG_ENV_SIZE
+# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE
+# endif
+# ifndef CFG_ENV_SECT_SIZE
+# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE
+# endif
+#endif
+
+/*---------------------------------------------------------------------*/
+#undef DEBUG_FLASH
+
+#ifdef DEBUG_FLASH
+#define DEBUGF(fmt,args...) printf(fmt ,##args)
+#else
+#define DEBUGF(fmt,args...)
+#endif
+/*---------------------------------------------------------------------*/
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_data (flash_info_t *info, ulong dest, ulong data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile memctl8xx_t *memctl = &immap->im_memctl;
+ unsigned long size_b0, size_b1;
+ int i;
+
+ /* Init: no FLASHes known */
+ for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ }
+
+ /* Static FLASH Bank configuration here - FIXME XXX */
+
+ DEBUGF("\n## Get flash bank 1 size @ 0x%08x\n",FLASH_BASE0_PRELIM);
+
+ size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+ if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+ printf ("## Unknown FLASH on Bank 0: "
+ "ID 0x%lx, Size = 0x%08lx = %ld MB\n",
+ flash_info[0].flash_id,
+ size_b0, size_b0<<20);
+ }
+
+ DEBUGF("## Get flash bank 2 size @ 0x%08x\n",FLASH_BASE1_PRELIM);
+
+ size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]);
+
+ DEBUGF("## Prelim. Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1);
+
+ if (size_b1 > size_b0) {
+ printf ("## ERROR: "
+ "Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n",
+ size_b1, size_b1<<20,
+ size_b0, size_b0<<20
+ );
+ flash_info[0].flash_id = FLASH_UNKNOWN;
+ flash_info[1].flash_id = FLASH_UNKNOWN;
+ flash_info[0].sector_count = -1;
+ flash_info[1].sector_count = -1;
+ flash_info[0].size = 0;
+ flash_info[1].size = 0;
+ return (0);
+ }
+
+ DEBUGF ("## Before remap: "
+ "BR0: 0x%08x OR0: 0x%08x "
+ "BR1: 0x%08x OR1: 0x%08x\n",
+ memctl->memc_br0, memctl->memc_or0,
+ memctl->memc_br1, memctl->memc_or1);
+
+ /* Remap FLASH according to real size */
+ memctl->memc_or0 = (-size_b0 & 0xFFFF8000) | CFG_OR_TIMING_FLASH |
+ OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI;
+ memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_PS_32 | BR_V;
+
+ DEBUGF("## BR0: 0x%08x OR0: 0x%08x\n",
+ memctl->memc_br0, memctl->memc_or0);
+
+ /* Re-do sizing to get full correct info */
+ size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+
+ flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+
+ flash_info[0].size = size_b0;
+
+ /* monitor protection ON by default */
+ flash_protect(FLAG_PROTECT_SET,
+ CFG_FLASH_BASE,
+ CFG_FLASH_BASE+CFG_MONITOR_LEN-1,
+ &flash_info[0]);
+
+#ifdef CFG_ENV_IS_IN_FLASH
+ /* ENV protection ON by default */
+ flash_protect(FLAG_PROTECT_SET,
+ CFG_ENV_ADDR,
+ CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1,
+ &flash_info[0]);
+#endif
+
+ if (size_b1) {
+ memctl->memc_or1 = (-size_b1 & 0xFFFF8000) | CFG_OR_TIMING_FLASH |
+ OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI;
+ memctl->memc_br1 = ((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) |
+ BR_PS_32 | BR_V;
+
+ DEBUGF("## BR1: 0x%08x OR1: 0x%08x\n",
+ memctl->memc_br1, memctl->memc_or1);
+
+ /* Re-do sizing to get full correct info */
+ size_b1 = flash_get_size((vu_long *)(CFG_FLASH_BASE + size_b0),
+ &flash_info[1]);
+
+ flash_info[1].size = size_b1;
+
+ flash_get_offsets (CFG_FLASH_BASE + size_b0, &flash_info[1]);
+
+ /* monitor protection ON by default */
+ flash_protect(FLAG_PROTECT_SET,
+ CFG_FLASH_BASE,
+ CFG_FLASH_BASE+CFG_MONITOR_LEN-1,
+ &flash_info[1]);
+
+#ifdef CFG_ENV_IS_IN_FLASH
+ /* ENV protection ON by default */
+ flash_protect(FLAG_PROTECT_SET,
+ CFG_ENV_ADDR,
+ CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1,
+ &flash_info[1]);
+#endif
+ } else {
+ memctl->memc_br1 = 0; /* invalidate bank */
+ memctl->memc_or1 = 0; /* invalidate bank */
+
+ DEBUGF("## DISABLE BR1: 0x%08x OR1: 0x%08x\n",
+ memctl->memc_br1, memctl->memc_or1);
+
+ flash_info[1].flash_id = FLASH_UNKNOWN;
+ flash_info[1].sector_count = -1;
+ flash_info[1].size = 0;
+ }
+
+ DEBUGF("## Final Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1);
+
+ return (size_b0 + size_b1);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+ int i;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ return;
+ }
+
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case FLASH_MAN_INTEL:
+ for (i = 0; i < info->sector_count; i++) {
+ info->start[i] = base;
+ base += 0x00020000;
+ }
+ return;
+
+ default:
+ printf ("Don't know sector ofsets for flash type 0x%lx\n",
+ info->flash_id);
+ return;
+ }
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t *info)
+{
+ int i;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("missing or unknown FLASH type\n");
+ return;
+ }
+
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case FLASH_MAN_AMD: printf ("AMD "); break;
+ case FLASH_MAN_FUJ: printf ("Fujitsu "); break;
+ case FLASH_MAN_SST: printf ("SST "); break;
+ case FLASH_MAN_STM: printf ("STM "); break;
+ case FLASH_MAN_INTEL: printf ("Intel "); break;
+ case FLASH_MAN_MT: printf ("MT "); break;
+ default: printf ("Unknown Vendor "); break;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_28F320JA3: printf ("28F320JA3 (32Mbit = 128K x 32)\n");
+ break;
+ case FLASH_28F640JA3: printf ("28F640JA3 (64Mbit = 128K x 64)\n");
+ break;
+ case FLASH_28F128JA3: printf ("28F128JA3 (128Mbit = 128K x 128)\n");
+ break;
+ default: printf ("Unknown Chip Type\n");
+ break;
+ }
+
+ if (info->size >= (1 << 20)) {
+ i = 20;
+ } else {
+ i = 10;
+ }
+ printf (" Size: %ld %cB in %d Sectors\n",
+ info->size >> i,
+ (i == 20) ? 'M' : 'k',
+ info->sector_count);
+
+ printf (" Sector Start Addresses:");
+ for (i=0; i<info->sector_count; ++i) {
+ if ((i % 5) == 0)
+ printf ("\n ");
+ printf (" %08lX%s",
+ info->start[i],
+ info->protect[i] ? " (RO)" : " "
+ );
+ }
+ printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+ ulong value;
+
+ /* Read Manufacturer ID */
+ addr[0] = 0x00900090;
+ value = addr[0];
+
+ DEBUGF("Manuf. ID @ 0x%08lx: 0x%08lx\n", (ulong)addr, value);
+
+ switch (value) {
+ case AMD_MANUFACT:
+ info->flash_id = FLASH_MAN_AMD;
+ break;
+ case FUJ_MANUFACT:
+ info->flash_id = FLASH_MAN_FUJ;
+ break;
+ case SST_MANUFACT:
+ info->flash_id = FLASH_MAN_SST;
+ break;
+ case STM_MANUFACT:
+ info->flash_id = FLASH_MAN_STM;
+ break;
+ case INTEL_MANUFACT:
+ info->flash_id = FLASH_MAN_INTEL;
+ break;
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ addr[0] = 0x00FF00FF; /* restore read mode */
+ return (0); /* no or unknown flash */
+ }
+
+ value = addr[1]; /* device ID */
+
+ DEBUGF("Device ID @ 0x%08lx: 0x%08lx\n", (ulong)(&addr[1]), value);
+
+ switch (value) {
+ case INTEL_ID_28F320JA3:
+ info->flash_id += FLASH_28F320JA3;
+ info->sector_count = 32;
+ info->size = 0x00400000;
+ break; /* => 1 MB */
+
+ case INTEL_ID_28F640JA3:
+ info->flash_id += FLASH_28F640JA3;
+ info->sector_count = 64;
+ info->size = 0x00800000;
+ break; /* => 1 MB */
+
+ case INTEL_ID_28F128JA3:
+ info->flash_id += FLASH_28F128JA3;
+ info->sector_count = 128;
+ info->size = 0x01000000;
+ break; /* => 2 MB */
+
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ addr[0] = 0x00FF00FF; /* restore read mode */
+ return (0); /* => no or unknown flash */
+
+ }
+
+ if (info->sector_count > CFG_MAX_FLASH_SECT) {
+ printf ("** ERROR: sector count %d > max (%d) **\n",
+ info->sector_count, CFG_MAX_FLASH_SECT);
+ info->sector_count = CFG_MAX_FLASH_SECT;
+ }
+
+ addr[0] = 0x00FF00FF; /* restore read mode */
+
+ return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+void flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+ int flag, prot, sect;
+ ulong start, now, last;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("- missing\n");
+ } else {
+ printf ("- no sectors to erase\n");
+ }
+ return;
+ }
+
+ if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) {
+ printf ("Can erase only Intel flash types - aborted\n");
+ return;
+ }
+
+ prot = 0;
+ for (sect=s_first; sect<=s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+
+ if (prot) {
+ printf ("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ } else {
+ printf ("\n");
+ }
+
+ start = get_timer (0);
+ last = start;
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect<=s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ vu_long *addr = (vu_long *)(info->start[sect]);
+ unsigned long status;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ *addr = 0x00500050; /* clear status register */
+ *addr = 0x00200020; /* erase setup */
+ *addr = 0x00D000D0; /* erase confirm */
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* wait at least 80us - let's wait 1 ms */
+ udelay (1000);
+
+ while (((status = *addr) & 0x00800080) != 0x00800080) {
+ if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+ printf ("Timeout\n");
+ *addr = 0x00B000B0; /* suspend erase */
+ *addr = 0x00FF00FF; /* reset to read mode */
+ return;
+ }
+
+ /* show that we're waiting */
+ if ((now - last) > 1000) { /* every second */
+ putc ('.');
+ last = now;
+ }
+ }
+
+ *addr = 0x00FF00FF; /* reset to read mode */
+ }
+ }
+ printf (" done\n");
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+#define FLASH_WIDTH 4 /* flash bus width in bytes */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+ ulong cp, wp, data;
+ int i, l, rc;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ return 4;
+ }
+
+ wp = (addr & ~(FLASH_WIDTH-1)); /* get lower FLASH_WIDTH aligned address */
+
+ /*
+ * handle unaligned start bytes
+ */
+ if ((l = addr - wp) != 0) {
+ data = 0;
+ for (i=0, cp=wp; i<l; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+ for (; i<FLASH_WIDTH && cnt>0; ++i) {
+ data = (data << 8) | *src++;
+ --cnt;
+ ++cp;
+ }
+ for (; cnt==0 && i<FLASH_WIDTH; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+
+ if ((rc = write_data(info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += FLASH_WIDTH;
+ }
+
+ /*
+ * handle FLASH_WIDTH aligned part
+ */
+ while (cnt >= FLASH_WIDTH) {
+ data = 0;
+ for (i=0; i<FLASH_WIDTH; ++i) {
+ data = (data << 8) | *src++;
+ }
+ if ((rc = write_data(info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += FLASH_WIDTH;
+ cnt -= FLASH_WIDTH;
+ }
+
+ if (cnt == 0) {
+ return (0);
+ }
+
+ /*
+ * handle unaligned tail bytes
+ */
+ data = 0;
+ for (i=0, cp=wp; i<FLASH_WIDTH && cnt>0; ++i, ++cp) {
+ data = (data << 8) | *src++;
+ --cnt;
+ }
+ for (; i<FLASH_WIDTH; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+
+ return (write_data(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t *info, ulong dest, ulong data)
+{
+ vu_long *addr = (vu_long *)dest;
+ ulong status;
+ ulong start;
+ int flag;
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*addr & data) != data) {
+ return (2);
+ }
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ *addr = 0x00400040; /* write setup */
+ *addr = data;
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ start = get_timer (0);
+
+ while (((status = *addr) & 0x00800080) != 0x00800080) {
+ if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+ *addr = 0x00FF00FF; /* restore read mode */
+ return (1);
+ }
+ }
+
+ *addr = 0x00FF00FF; /* restore read mode */
+
+ return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
--- /dev/null
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * Ulrich Lutz, Speech Design GmbH, ulutz@datalab.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppcboot.h>
+#include <mpc8xx.h>
+#include <commproc.h>
+
+/* ------------------------------------------------------------------------- */
+
+static long int dram_size (long int, long int *, long int);
+
+/* ------------------------------------------------------------------------- */
+
+#define _NOT_USED_ 0xFFFFFFFF
+
+/*
+ * 66 MHz SDRAM access using UPM A
+ */
+const uint sdram_table[] =
+{
+ /*
+ * Single Read. (Offset 0 in UPM RAM)
+ */
+ 0x1F0DFC04, 0xEEAFBC04, 0x11AF7C04, 0xEFBAFC00,
+ 0x1FF5FC47, /* last */
+ /*
+ * SDRAM Initialization (offset 5 in UPM RAM)
+ *
+ * This is no UPM entry point. The following definition uses
+ * the remaining space to establish an initialization
+ * sequence, which is executed by a RUN command.
+ *
+ */
+ 0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */
+ /*
+ * Burst Read. (Offset 8 in UPM RAM)
+ */
+ 0x1F0DFC04, 0xEEAFBC04, 0x10AF7C04, 0xF0AFFC00,
+ 0xF0AFFC00, 0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ /*
+ * Single Write. (Offset 18 in UPM RAM)
+ */
+ 0x1F2DFC04, 0xEEABBC00, 0x01B27C04, 0x1FF5FC47, /* last */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ /*
+ * Burst Write. (Offset 20 in UPM RAM)
+ */
+ 0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00,
+ 0xF0AFFC00, 0xE1BAFC04, 0x01FF5FC47, /* last */
+ _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ /*
+ * Refresh (Offset 30 in UPM RAM)
+ */
+ 0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
+ 0xFFFFFC84, 0xFFFFFC07, /* last */
+ _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ /*
+ * Exception. (Offset 3c in UPM RAM)
+ */
+ 0x7FFFFC07, /* last */
+ 0xFFFFFCFF, 0xFFFFFCFF, 0xFFFFFCFF,
+};
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Check Board Identity:
+ *
+ */
+
+int checkboard (void)
+{
+ printf ("Litronic Monitor IV\n");
+ return (1);
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int
+initdram (int board_type)
+{
+ volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ volatile memctl8xx_t *memctl = &immr->im_memctl;
+ long int size_b0;
+ int i;
+
+ /*
+ * Configure UPMA for SDRAM
+ */
+ upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
+
+ memctl->memc_mptpr = CFG_MPTPR;
+
+ /* burst length=4, burst type=sequential, CAS latency=2 */
+ memctl->memc_mar = 0x00000088;
+
+ /*
+ * Map controller bank 3 to the SDRAM bank at preliminary address.
+ */
+ memctl->memc_or3 = CFG_OR3_PRELIM;
+ memctl->memc_br3 = CFG_BR3_PRELIM;
+
+ /* initialize memory address register */
+ memctl->memc_mamr = CFG_MAMR; /* refresh not enabled yet */
+
+ /* mode initialization (offset 5) */
+ udelay(200); /* 0x80006105 */
+ memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x05);
+
+ /* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */
+ udelay(1); /* 0x80006130 */
+ memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x30);
+ udelay(1); /* 0x80006130 */
+ memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x30);
+
+ udelay(1); /* 0x80006106 */
+ memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x06);
+
+ memctl->memc_mamr |= MAMR_PTBE; /* refresh enabled */
+
+ udelay(200);
+
+ /* Need at least 10 DRAM accesses to stabilize */
+ for (i=0; i<10; ++i) {
+ volatile unsigned long *addr = (volatile unsigned long *)SDRAM_BASE3_PRELIM;
+ unsigned long val;
+
+ val = *(addr + i);
+ *(addr + i) = val;
+ }
+
+ /*
+ * Check Bank 0 Memory Size for re-configuration
+ */
+ size_b0 = dram_size (CFG_MAMR, (ulong *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
+
+ memctl->memc_mamr = CFG_MAMR | MAMR_PTBE;
+
+ return (size_b0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+
+static long int dram_size (long int mamr_value, long int *base, long int maxsize)
+{
+ volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ volatile memctl8xx_t *memctl = &immr->im_memctl;
+ volatile long int *addr;
+ long int cnt, val;
+
+ memctl->memc_mamr = mamr_value;
+
+ for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
+ addr = base + cnt; /* pointer arith! */
+
+ *addr = ~cnt;
+ }
+
+ /* write 0 to base address */
+ addr = base;
+ *addr = 0;
+
+ /* check at base address */
+ if ((val = *addr) != 0) {
+ return (0);
+ }
+
+ for (cnt = 1; ; cnt <<= 1) {
+ addr = base + cnt; /* pointer arith! */
+
+ val = *addr;
+
+ if (val != (~cnt)) {
+ return (cnt * sizeof(long));
+ }
+ }
+ /* NOTREACHED */
+}
+
+/* ------------------------------------------------------------------------- */
+
+void reset_phy(void)
+{
+ immap_t *immr = (immap_t *)CFG_IMMR;
+
+ printf ("### ADD CODE HERE to switch on Ethernet for SCC2 ###\n");
+ udelay(1000);
+}
--- /dev/null
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ cpu/mpc8xx/start.o (.text)
+ common/environment.o(.text)
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x0FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
+
--- /dev/null
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/mpc8xx/start.o (.text)
+ common/dlmalloc.o (.text)
+ ppc/vsprintf.o (.text)
+ ppc/crc32.o (.text)
+ ppc/extable.o (.text)
+
+ . = env_offset;
+ common/environment.o(.text)
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x0FFF) & 0xFFFFF000;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(4096);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(4096);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
+
* MA 02111-1307 USA
*/
-/* bits for control register #2 / status register #2 */
+/* bits for control register #1 / status register #1 */
#define CSR1_ETEN 0x80 /* Ethernet Transceiver Enabled */
#define CSR1_ELEN 0x40 /* Ethernet XCVR in Internal Loopback */
#define CSR1_EAEN 0x20 /* Auto selection TP/AUI Enabled */
#define CSR1_XCVRDIS 0x01 /* Onboard RS232 Transceiver Disabled */
/* bits for control register #2 */
-#define CR2_VDDSEL 0x03 /* PCMCIA Supply Voltage */
-#define CR2_VPPSEL 0x0c /* PCMCIA Programming Voltage */
-#define CR2_BRDFAIL 0x10 /* Board fail */
-#define CR2_SWS1 0x20 /* Software Status #2 LED */
-#define CR2_SWS2 0x40 /* Software Status #2 LED */
-#define CR2_QSPANRST 0x80 /* Reset QSPAN */
+#define CR2_VDDSEL 0xC0 /* PCMCIA Supply Voltage */
+#define CR2_VPPSEL 0x30 /* PCMCIA Programming Voltage */
+#define CR2_BRDFAIL 0x08 /* Board fail */
+#define CR2_SWS1 0x04 /* Software Status #2 LED */
+#define CR2_SWS2 0x02 /* Software Status #2 LED */
+#define CR2_QSPANRST 0x01 /* Reset QSPAN */
/* bits for status register #2 */
-#define SR2_VDDSEL 0x03 /* PCMCIA Supply Voltage */
-#define SR2_VPPSEL 0x0c /* PCMCIA Programming Voltage */
-#define SR2_BATGD 0x10 /* Low Voltage indication for onboard bat */
-#define SR2_NVBATGD 0x20 /* Low Voltage indication for NVRAM */
-#define SR2_RDY 0x40 /* Flash programming status bit */
-#define SR2_FT 0x80 /* Reserved for Factory test purposes */
+#define SR2_VDDSEL 0xC0 /* PCMCIA Supply Voltage */
+#define SR2_VPPSEL 0x30 /* PCMCIA Programming Voltage */
+#define SR2_BATGD 0x08 /* Low Voltage indication for onboard bat */
+#define SR2_NVBATGD 0x04 /* Low Voltage indication for NVRAM */
+#define SR2_RDY 0x02 /* Flash programming status bit */
+#define SR2_FT 0x01 /* Reserved for Factory test purposes */
#define MBX_CSR1 (*((uchar *)CFG_CSR_BASE))
#define MBX_CSR2 (*((uchar *)CFG_CSR_BASE + 1))
volatile immap_t *immr = (immap_t *)CFG_IMMR;
volatile memctl8xx_t *memctl = &immr->im_memctl;
ulong speed, refclock, plprcr, sccr;
+ ulong br0_32 = memctl->memc_br0 & 0x400;
/* real-time clock status and control register */
immr->im_sitk.sitk_rtcsck = KAPWR_KEY;
speed = board_get_cpufreq();
refclock = get_reffreq();
+#if ((CFG_PLPRCR & PLPRCR_MF_MSK) != 0)
plprcr = CFG_PLPRCR;
+#else
+ plprcr = immr->im_clkrst.car_plprcr;
+ plprcr &= PLPRCR_MF_MSK; /* isolate MF field */
+ plprcr |= CFG_PLPRCR; /* reset control bits */
+#endif
+#if 0 /* XXX - Just what was this for??? email etheisen@mindspring.com */
plprcr |= ((speed + refclock / 2) / refclock - 1) << 20;
+#endif
immr->im_clkrst.car_plprcr = plprcr;
/*
* preliminary setup of memory controller:
- * - map pci registers
- * - map configuation and status registers
- * - DON'T map ram/flash/rom yet, this is done in initdram()
+ * - map Flash, otherwise configuration/status
+ * registers won't be accessible when read
+ * by board_init_f.
+ * - map NVRAM and configuation/status registers.
+ * - map pci registers.
+ * - DON'T map ram yet, this is done in initdram().
*/
switch(speed / 1000000)
{
case 40:
- memctl->memc_br4 = CFG_NVRAM_BASE | 0x401;
+ memctl->memc_br0 = 0xfe000000 | br0_32 | 1;
+ memctl->memc_or0 = 0xff800930;
memctl->memc_or4 = CFG_NVRAM_OR | 0x920;
+ memctl->memc_br4 = CFG_NVRAM_BASE | 0x401;
break;
case 50:
- memctl->memc_br4 = CFG_NVRAM_BASE | 0x401;
+ memctl->memc_br0 = 0xfe000000 | br0_32 | 1;
+ memctl->memc_or0 = 0xff800940;
memctl->memc_or4 = CFG_NVRAM_OR | 0x930;
+ memctl->memc_br4 = CFG_NVRAM_BASE | 0x401;
break;
default:
hang();
break;
}
- memctl->memc_br5 = CFG_PCIMEM_BASE | 0x001;
memctl->memc_or5 = CFG_PCIMEM_OR;
- memctl->memc_br6 = CFG_PCIBRIDGE_BASE | 0x001;
+ memctl->memc_br5 = CFG_PCIMEM_BASE | 0x001;
memctl->memc_or6 = CFG_PCIBRIDGE_OR;
+ memctl->memc_br6 = CFG_PCIBRIDGE_BASE | 0x001;
}
void board_serial_init(void)
sizeof(sdram_table_40) / sizeof(uint));
memctl->memc_mptpr = 0x0200;
memctl->memc_mamr = dimm_sz ? 0x06801000 : 0x13801000;
- memctl->memc_br0 = 0xfe000000 | br0_32 | 1;
- memctl->memc_or0 = 0xff800930;
- memctl->memc_br7 = 0xfc000000 | (br0_32 ^ br0_32) | 1;
memctl->memc_or7 = 0xff800930;
+ memctl->memc_br7 = 0xfc000000 | (br0_32 ^ br0_32) | 1;
break;
case 50:
upmconfig(UPMA, (uint *)sdram_table_50,
sizeof(sdram_table_50) / sizeof(uint));
memctl->memc_mptpr = 0x0200;
memctl->memc_mamr = dimm_sz ? 0x08801000 : 0x1880100;
- memctl->memc_br0 = 0xfe000000 | br0_32 | 1;
- memctl->memc_or0 = 0xff800940;
- memctl->memc_br7 = 0xfc000000 | (br0_32 ^ br0_32) | 1;
memctl->memc_or7 = 0xff800940;
+ memctl->memc_br7 = 0xfc000000 | (br0_32 ^ br0_32) | 1;
break;
default:
hang();
dimm_bank = dimm_sz / 2;
if (!dimm_sz)
{
- memctl->memc_br1 = CFG_SDRAM_BASE | 0x81;
memctl->memc_or1 = ~(ram_sz - 1) | 0x400;
+ memctl->memc_br1 = CFG_SDRAM_BASE | 0x81;
memctl->memc_br2 = 0;
memctl->memc_br3 = 0;
}
else if (ram_sz > dimm_bank)
{
- memctl->memc_br1 = CFG_SDRAM_BASE | 0x81;
memctl->memc_or1 = ~(ram_sz - 1) | 0x400;
- memctl->memc_br2 = (CFG_SDRAM_BASE + ram_sz) | 0x81;
+ memctl->memc_br1 = CFG_SDRAM_BASE | 0x81;
memctl->memc_or2 = ~(dimm_bank - 1) | 0x400;
- memctl->memc_br3 = (CFG_SDRAM_BASE + ram_sz + dimm_bank) | 0x81;
+ memctl->memc_br2 = (CFG_SDRAM_BASE + ram_sz) | 0x81;
memctl->memc_or3 = ~(dimm_bank - 1) | 0x400;
+ memctl->memc_br3 = (CFG_SDRAM_BASE + ram_sz + dimm_bank) | 0x81;
}
else
{
- memctl->memc_br2 = CFG_SDRAM_BASE | 0x81;
memctl->memc_or2 = ~(dimm_bank - 1) | 0x400;
- memctl->memc_br3 = (CFG_SDRAM_BASE + dimm_bank) | 0x81;
+ memctl->memc_br2 = CFG_SDRAM_BASE | 0x81;
memctl->memc_or3 = ~(dimm_bank - 1) | 0x400;
- memctl->memc_br1 = (CFG_SDRAM_BASE + dimm_sz) | 0x81;
+ memctl->memc_br3 = (CFG_SDRAM_BASE + dimm_bank) | 0x81;
memctl->memc_or1 = ~(ram_sz - 1) | 0x400;
+ memctl->memc_br1 = (CFG_SDRAM_BASE + dimm_sz) | 0x81;
}
}
for (i=0; i<50; i++)
udelay(1000); /* wait 1 ms */
} else {
+ if (sect == s_first) {
addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080;
addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+ }
addr2[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */
}
l_sect = sect;
/* Pointer to initial global data area */
init_data_t *idata = (init_data_t *)(CFG_INIT_RAM_ADDR + CFG_INIT_DATA_OFFSET);
-#if defined(CONFIG_CPCI405) || defined(CONFIG_AR405) || \
- defined(CONFIG_CANBT) || defined(CONFIG_WALNUT405)
+#if defined(CONFIG_CPCI405) || \
+ defined(CONFIG_AR405) || \
+ defined(CONFIG_CANBT) || \
+ defined(CONFIG_WALNUT405) || \
+ defined(CONFIG_CPCIISER4) || \
+ defined(CONFIG_ADCIOP)
board_pre_init(); /* very early board init code (fpga boot, etc.) */
#endif
*/
init_timebase ();
- env_init (idata);
-
- i = getenv_r ("baudrate", tmp, sizeof(tmp));
- baudrate = (i > 0) ? (int)simple_strtoul(tmp, NULL, 10) : CONFIG_BAUDRATE;
-
#ifdef CFG_ALLOC_DPRAM
/*
* set up dual port ram alloc area
dpram_init ();
#endif
+#if defined(CONFIG_HYMOD)
+ /*
+ * this initialisation is for very early stuff that requires the i2c
+ * driver (which needs to know the clocks, to calculate the dividers,
+ * and timebase, for udelay(), and dual port ram on the 8xx platform)
+ */
+ board_postclk_init();
+#endif
+
+ env_init (idata);
+
+ i = getenv_r ("baudrate", tmp, sizeof(tmp));
+ baudrate = (i > 0) ? (int)simple_strtoul(tmp, NULL, 10) : CONFIG_BAUDRATE;
+
/* set up serial port */
serial_init (idata->cpu_clk, baudrate);
hang();
}
-#if defined(CONFIG_COGENT) || defined(CONFIG_SXNI855T) || defined(CONFIG_RSD_PROTO)
+#if defined(CONFIG_COGENT) || defined(CONFIG_SXNI855T) || \
+ defined(CONFIG_RSD_PROTO) || defined(CONFIG_HYMOD)
/* miscellaneous platform dependent initialisations */
if (misc_init_f() < 0) {
puts (failed);
/* relocate environment function pointers etc. */
env_relocate (reloc_off);
-#ifdef CONFIG_COGENT
+#if defined(CONFIG_COGENT) || defined(CONFIG_HYMOD)
/* miscellaneous platform dependent initialisations */
misc_init_r(bd);
#endif
#if defined(CONFIG_SPD823TS) || \
defined(CONFIG_IVMS8) || \
defined(CONFIG_IVML24) || \
- defined(CONFIG_IP860)
+ defined(CONFIG_IP860) || \
+ defined(CONFIG_LWMON)
# ifdef DEBUG
puts (" Reset Ethernet PHY\n");
# endif
#endif /* CFG_CMD_NET */
/* Initialize other board modules */
-#ifdef CONFIG_PCI_PNP
+#ifdef CONFIG_PCI
/*
- * Do pci plug-n-play configuration
+ * Do pci configuration
*/
pci_init();
#endif
#undef I2C_DEBUG
#ifdef I2C_DEBUG
-#define PRINTF(fmt,args...) do { \
- printf (fmt ,##args); \
- } while (0)
+#define PRINTF(fmt,args...) printf (fmt ,##args)
#else
#define PRINTF(fmt,args...)
#endif
unsigned char i2c_addr, sec_addr, *data_addr;
unsigned short size;
int speed;
-#ifdef CONFIG_MPC8260
i2c_state_t state;
int rc;
-#endif
switch (argc) {
case 2:
if (strncmp(argv[1], "res", 3) == 0) {
printf("\nI2C reset 50kHz ... ");
-#ifdef CONFIG_MPC8260
i2c_init(50000, 0xfe); /* use all one's as slave address */
-#else
- i2c_init ();
-#endif
printf("DONE\n");
return;
}
printf("\nI2C reset %d.%03dkHz ... ", speed/1000, speed%1000);
else
printf("\nI2C reset %dkHz ... ", speed/1000);
-#ifdef CONFIG_MPC8260
i2c_init(speed, 0xfe); /* use all one's as slave address */
-#else
- i2c_init ();
-#endif
printf("DONE\n");
return;
}
printf("\nI2C recv: i2c_addr 0x%02x, data_addr 0x%08lx, "
"size %u ... ", i2c_addr, (ulong)data_addr, size);
-#ifdef CONFIG_MPC8260
+
i2c_newio(&state);
rc = i2c_receive(&state, i2c_addr, 0,
printf("FAILED (i2c_doio return code = %d)\n", rc);
return;
}
-#else
- i2c_receive(i2c_addr, 0, 0, size, data_addr);
-#endif
+
printf("DONE\n");
return;
}
printf("\nI2C send: i2c_addr 0x%02x, data_addr 0x%08lx, "
"size %u ... ", i2c_addr, (ulong)data_addr, size);
-#ifdef CONFIG_MPC8260
+
i2c_newio(&state);
rc = i2c_send(&state, i2c_addr, 0,
printf("FAILED (i2c_doio return code = %d)\n", rc);
return;
}
-#else
- i2c_send(i2c_addr, 0, 0, size, data_addr);
-#endif
+
printf("DONE\n");
return;
}
printf("\nI2C recv: i2c_addr 0x%02x, sec_addr 0x%02x, "
"data_addr 0x%08lx, size %u ... ",
i2c_addr, sec_addr, (ulong)data_addr, size);
-#ifdef CONFIG_MPC8260
+
i2c_newio(&state);
rc = i2c_receive(&state, i2c_addr, sec_addr,
printf("FAILED (i2c_doio return code = %d)\n", rc);
return;
}
-#else
- i2c_receive(i2c_addr, sec_addr, 1, size, data_addr);
-#endif
+
printf("DONE\n");
return;
}
printf("\nI2C send: i2c_addr 0x%02x, sec_addr 0x%02x, "
"data_addr 0x%08lx, size %u ... ",
i2c_addr, sec_addr, (ulong)data_addr, size);
-#ifdef CONFIG_MPC8260
+
i2c_newio(&state);
rc = i2c_receive(&state, i2c_addr, sec_addr,
printf("FAILED (i2c_doio return code = %d)\n", rc);
return;
}
-#else
- i2c_send(i2c_addr, sec_addr, 1, size, data_addr);
-#endif
+
printf("DONE\n");
return;
}
#undef DEBUG_ENV
#ifdef DEBUG_ENV
-#define DEBUG(fmt,args...) printf(fmt ,##args)
+#define DEBUGF(fmt,args...) printf(fmt ,##args)
#else
-#define DEBUG(fmt,args...)
+#define DEBUGF(fmt,args...)
#endif
/*---------------------------------------------------------------------*/
{
init_data_t *idata = (init_data_t*)(CFG_INIT_RAM_ADDR+CFG_INIT_DATA_OFFSET);
- DEBUG ("%s[%d] offset = 0x%lx\n", __FUNCTION__,__LINE__,offset);
+ DEBUGF ("%s[%d] offset = 0x%lx\n", __FUNCTION__,__LINE__,offset);
#if !defined(ENV_IS_EMBEDDED) || defined(CFG_ENV_IS_IN_NVRAM)
/*
* We must allocate a buffer for the environment
* so we need a RAM copy here, too.
*/
env_ptr = (env_t *)malloc (CFG_ENV_SIZE);
- DEBUG ("%s[%d] malloced ENV at %p\n", __FUNCTION__,__LINE__,env_ptr);
+ DEBUGF ("%s[%d] malloced ENV at %p\n", __FUNCTION__,__LINE__,env_ptr);
#else /* ENV_IS_EMBEDDED */
/*
* The environment buffer is embedded with the text segment,
* just relocate the environment pointer
*/
env_ptr = (env_t *)((ulong)env_ptr + offset);
- DEBUG ("%s[%d] embedded ENV at %p\n", __FUNCTION__,__LINE__,env_ptr);
+ DEBUGF ("%s[%d] embedded ENV at %p\n", __FUNCTION__,__LINE__,env_ptr);
#endif
/*
}
#if !defined(ENV_IS_EMBEDDED)
else {
- DEBUG ("%s[%d] ENV is valid\n", __FUNCTION__,__LINE__);
+ DEBUGF ("%s[%d] ENV is valid\n", __FUNCTION__,__LINE__);
# if defined(CFG_ENV_IS_IN_EEPROM)
- DEBUG ("%s[%d] read ENV from EEPROM\n", __FUNCTION__,__LINE__);
+ DEBUGF ("%s[%d] read ENV from EEPROM\n", __FUNCTION__,__LINE__);
eeprom_read (offsetof(env_t,data), env_ptr->data, ENV_SIZE);
# else
- DEBUG ("%s[%d] read ENV from NVRAM/FLASH\n", __FUNCTION__,__LINE__);
+ DEBUGF ("%s[%d] read ENV from NVRAM/FLASH\n",__FUNCTION__,__LINE__);
memcpy (env_ptr->data,
((env_t *)CFG_ENV_ADDR)->data,
ENV_SIZE);
win->or = ( PCMCIA_BSIZE_64M
| PCMCIA_PPS_8
| PCMCIA_PRS_ATTR
- | PCMCIA_PSLOT_B
+ | PCMCIA_SLOT_x
| PCMCIA_PV
| 0x00024480 ); /* fixed access timing */
break;
win->or = ( PCMCIA_BSIZE_1K
| PCMCIA_PPS_16
| PCMCIA_PRS_IO
- | PCMCIA_PSLOT_B
+ | PCMCIA_SLOT_x
| PCMCIA_PV
| 0x00024480 ); /* fixed access timing */
break;
win->or = ( PCMCIA_BSIZE_1K
| PCMCIA_PPS_8
| PCMCIA_PRS_IO
- | PCMCIA_PSLOT_B
+ | PCMCIA_SLOT_x
| PCMCIA_PV
| 0x00024480 ); /* fixed access timing */
break;
#endif /* TQM8xxL */
+/* ---------------------------------------------------------------------------- */
+/* GTH board by Corelatus AB */
+/* ---------------------------------------------------------------------------- */
+#if defined(CONFIG_GTH)
+
+#define PCMCIA_BOARD_MSG "GTH COMPACT FLASH"
+
+static int voltage_set(int slot, int vcc, int vpp)
+{ /* Do nothing */
+ return 0;
+}
+
+static int hardware_enable (int slot)
+{
+ volatile immap_t *immap;
+ volatile cpm8xx_t *cp;
+ volatile pcmconf8xx_t *pcmp;
+ volatile sysconf8xx_t *sysp;
+ uint reg, mask;
+
+ PCMCIA_DEBUG ("hardware_enable: GTH Slot %c\n", 'A'+slot);
+
+ immap = (immap_t *)CFG_IMMR;
+ sysp = (sysconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_siu_conf));
+ pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
+ cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
+
+ /* clear interrupt state, and disable interrupts */
+ pcmp->pcmc_pscr = PCMCIA_MASK(_slot_);
+ pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_);
+
+ /* disable interrupts & DMA */
+ PCMCIA_PGCRX(_slot_) = 0;
+
+ /*
+ * Disable PCMCIA buffers (isolate the interface)
+ * and assert RESET signal
+ */
+ PCMCIA_DEBUG ("Disable PCMCIA buffers and assert RESET\n");
+ reg = PCMCIA_PGCRX(_slot_);
+ reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
+ reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
+ PCMCIA_PGCRX(_slot_) = reg;
+ udelay(500);
+
+ /*
+ * Make sure there is a card in the slot, then configure the interface.
+ */
+ udelay(10000);
+ PCMCIA_DEBUG ("[%d] %s: PIPR(%p)=0x%x\n",
+ __LINE__,__FUNCTION__,
+ &(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
+ if (pcmp->pcmc_pipr & 0x98000000) {
+ printf (" No Card found\n");
+ return (1);
+ }
+
+ mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot);
+ reg = pcmp->pcmc_pipr;
+ PCMCIA_DEBUG ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n",
+ reg,
+ (reg&PCMCIA_VS1(slot))?"n":"ff",
+ (reg&PCMCIA_VS2(slot))?"n":"ff");
+
+ PCMCIA_DEBUG ("Enable PCMCIA buffers and stop RESET\n");
+ reg = PCMCIA_PGCRX(_slot_);
+ reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
+ reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
+ PCMCIA_PGCRX(_slot_) = reg;
+
+ udelay(250000); /* some cards need >150 ms to come up :-( */
+
+ PCMCIA_DEBUG ("# hardware_enable done\n");
+
+ return 0;
+}
+#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
+static int hardware_disable(int slot)
+{
+ return 0; /* No hardware to disable */
+}
+#endif /* CFG_CMD_PCMCIA */
+#endif /* CONFIG_GTH */
/* ---------------------------------------------------------------------------- */
/* End of Board Specific Stuff */
#include <cmd_i2c.h>
#include <cmd_immap.h>
#ifdef CONFIG_HYMOD
-#include <../board/hymod/cmd_fpga.h>
+#include <board/hymod/cmd_fpga.h>
#endif
/*
CMD_TBL_SIUINFO
CMD_TBL_MEMCINFO
CMD_TBL_SITINFO
+#ifdef CONFIG_8260
CMD_TBL_ICINFO
+#endif
CMD_TBL_CARINFO
CMD_TBL_IOPINFO
CMD_TBL_DMAINFO
}
// test if ctrl-c was pressed.
+static int ctrlc_was_pressed = 0;
int
ctrlc(void)
{
if (tstc()) {
switch (getc()) {
case 0x03: /* ^C - Control C */
+ ctrlc_was_pressed = 1;
return 1;
default:
}
return 0;
}
+int
+had_ctrlc(void)
+{
+ return ctrlc_was_pressed;
+}
+
+void
+clear_ctrlc(void)
+{
+ ctrlc_was_pressed = 0;
+}
+
//** PPCBOOT INIT FUNCTIONS *************************************************
int console_assign (int file, char *devname)
eputs("Cannot initialize the list of devices!\n");
return -1 ;
}
-#if defined(CONFIG_I2C) && !defined(CONFIG_MPC8260)
+#if defined(CONFIG_I2C) && !defined(CONFIG_8xx) && !defined(CONFIG_8260)
i2c_init();
#endif
#ifdef CONFIG_VIDEO
/****************************************************************************/
-static void process_macros (char *input, char *output)
+static void process_macros (const char *input, char *output)
{
- char c, prev, *varname_start;
+ char c, prev;
+ const char *varname_start;
int inputcnt = strlen (input);
int outputcnt = CFG_CBSIZE;
int state = 0; /* 0 = waiting for '$' */
* 0 - command executed but not repeatable, interrupted commands are
* always considered not repeatable
* -1 - not executed (unrecognized, bootd recursion or too many args)
- * (If cmd is NULL or "" it is considered unrecognized)
+ * (If cmd is NULL or "" or longer than CFG_CBSIZE-1 it is
+ * considered unrecognized)
+ *
+ * WARNING:
+ *
+ * We must create a temporary copy of the command since the command we get
+ * may be the result from getenv(), which returns a pointer directly to
+ * the environment data, which may change magicly when the command we run
+ * creates or modifies environment variables (like "bootp" does).
*/
+
int run_command (const char *cmd, bd_t *bd, int flag)
{
cmd_tbl_t *cmdtp;
- char token[CFG_CBSIZE];
+ char cmdbuf[CFG_CBSIZE]; /* working copy of cmd */
+ char *token; /* start of token in cmdbuf */
+ char *sep; /* end of token (separator) in cmdbuf */
char finaltoken[CFG_CBSIZE];
- const char *str = cmd;
+ char *str = cmdbuf;
char *argv[CFG_MAXARGS + 1]; /* NULL terminated */
int argc;
int repeatable = 1;
#ifdef DEBUG_PARSER
printf ("[RUN_COMMAND] cmd[%p]=\"%s\"\n", cmd, cmd ? cmd : "NULL");
#endif
- if (!cmd || !*cmd)
- return -1; /* empty command, do nothing */
+ if (!cmd || !*cmd || strlen(cmd) > CFG_CBSIZE - 1)
+ return -1; /* empty command or too long, do nothing */
+
+ strcpy (cmdbuf, cmd);
/* Process separators and check for invalid
* repeatable commands
printf ("[PROCESS_SEPARATORS] %s\n", cmd);
#endif
while (*str) {
- const char *sep;
- char *t;
/*
* Find separator, or string end
}
/*
- * Extract the token between separators
+ * Limit the token to data between separators
*/
- for (t = token; str < sep;) {
- *t++ = *str++;
- if (t >= token + CFG_CBSIZE - 1)
- break; /* just in case */
+ token = str;
+ if (*sep) {
+ str = sep + 1; /* start of command for next pass */
+ *sep = '\0';
}
- *t = '\0';
+ else
+ str = sep; /* no more commands for next pass */
#ifdef DEBUG_PARSER
printf ("token: \"%s\"\n", token);
#endif
/* Did the user stop this? */
if (tstc ())
return 0; /* if stopped then not repeatable */
-
- if (*sep != '\0')
- ++str;
}
return repeatable;
/****************************************************************************/
-/* WARNING:
- *
- * We must create a temporary copy of each value we get from
- * getenv(), since getenv() returns a pointer directly to the
- * environment data, which may change magicly when the command we run
- * creates or modifies environment variables (like "bootp" does).
- */
-
#if (CONFIG_COMMANDS & CFG_CMD_RUN)
void do_run (cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
{
}
for (i=1; i<argc; ++i) {
- char arg_buf[CFG_CBSIZE];
- char *val = getenv (argv[i]);
- if (val) {
- strcpy (arg_buf, val);
- val = arg_buf;
- }
- run_command (val, bd, flag);
+ run_command (getenv (argv[i]), bd, flag);
}
}
#endif
volatile memctl8xx_t *memctl = &immr->im_memctl;
ulong reg;
#endif
+#if defined(CONFIG_I2C) && defined(CFG_ALLOC_DPRAM)
+ volatile cpm8xx_t *cp = (cpm8xx_t *)&immr->im_cpm;
+ volatile iic_t *iip = (iic_t *)&cp->cp_dparam[PROFF_IIC];
+#endif
/* SYPCR - contains watchdog control (11-9) */
defined(CONFIG_IVML24) || \
defined(CONFIG_HERMES) || \
defined(CONFIG_IP860) || \
+ defined(CONFIG_LWMON) || \
defined(CONFIG_SXNI855T) || \
defined(CONFIG_RPXLITE) || \
+ defined(CONFIG_GTH) || \
(defined(CONFIG_MPC860T) && defined(CONFIG_FADS))
/* XXX - FIXME - XXX
* I still don't understand why some systems work only with this
*/
mbx_init();
#endif /* CONFIG_MBX */
+
+#if defined(CONFIG_I2C) && defined(CFG_ALLOC_DPRAM)
+ iip->iic_rbase = 0;
+#endif
}
/*
#include <commproc.h>
#include <i2c.h>
-// **********************************
-// ** DEBUG MACROS
-// **********************************
-
-//#define CONFIG_I2C_DEBUG
-#define DELAY_US 100000 // us to wait before checking the I2c
-
-// **********************************
-// ** CONSTANTS
-// **********************************
-
-#define CPCR_FLAG 0x01
-#define I2C_CPCR_CMD ( ( 0<<(15-7) ) | ( 1 << (15-11) ) | CPCR_FLAG )
-#define I2C_RX_LEN 128 /* Receive buffer length */
-#define I2C_TX_LEN 128 /* Transmit buffer length */
-#define TXBD_R 0x8000 /* Transmit buffer ready to send */
-#define TXBD_W 0x2000 /* Wrap, last buffer in buffer circle */
-#define TXBD_L 0x0800 /* Last, this buffer is the last in this frame */
- /* This bit causes the STOP condition to be sent */
-#define TXBD_S 0x0400 /* Start condition. Causes this BD to transmit a start */
-#define RXBD_E 0x8000 /* Receive buffer is empty and can be used by CPM */
-#define RXBD_W 0x2000 /* Wrap, last receive buffer in buffer circle */
-
-// **********************************
-// ** VARIABLES
-// **********************************
+/* define to enable debug messages */
+#define DEBUG_I2C
-#ifdef CFG_ALLOC_DPRAM
-static unsigned char *rxbuf, *txbuf;
+/* us to wait before checking the i2c */
+#define DELAY_US 100000
+
+/* tx/rx timeout (we need the i2c early, so we don't use get_timer()) */
+#define TOUT_LOOP 1000000
+
+#define NUM_RX_BDS 4
+#define NUM_TX_BDS 4
+#define MAX_TX_SPACE 256
+
+typedef struct I2C_BD
+{
+ unsigned short status;
+ unsigned short length;
+ unsigned char *addr;
+} I2C_BD;
+#define BD_I2C_TX_START 0x0400 /* special status for i2c: Start condition */
+
+#ifdef DEBUG_I2C
+#define PRINTD(x) printf x
#else
-static unsigned char rxbuf[I2C_RX_LEN], *txbuf[I2C_TX_LEN];
+#define PRINTD(x)
#endif
-static cbd_t *rxbd, *txbd;
+/*
+ * Returns the best value of I2BRG to meet desired clock speed of I2C with
+ * input parameters (clock speed, filter, and predivider value).
+ * It returns computer speed value and the difference between it and desired
+ * speed.
+ */
+static inline int
+i2c_roundrate(int hz, int speed, int filter, int modval,
+ int *brgval, int *totspeed)
+{
+ int moddiv = 1 << (5-(modval & 3)), brgdiv, div;
-volatile i2c8xx_t *i2c;
-volatile cbd_t *tbdf, *rbdf;
-volatile iic_t *iip;
+ PRINTD(("\t[I2C] trying hz=%d, speed=%d, filter=%d, modval=%d\n",
+ hz, speed, filter, modval));
-// **********************************
-// ** FUNCTIONS
-// **********************************
+ div = moddiv * speed;
+ brgdiv = (hz + div - 1) / div;
+
+ PRINTD(("\t\tmoddiv=%d, brgdiv=%d\n", moddiv, brgdiv));
+
+ *brgval = (brgdiv / 2) - 3 - (2*filter);
+
+ if ((*brgval < 0) || (*brgval > 255)) {
+ PRINTD(("\t\trejected brgval=%d\n", *brgval));
+ return -1;
+ }
+
+ brgdiv = 2 * (*brgval + 3 + (2 * filter));
+ div = moddiv * brgdiv ;
+ *totspeed = (hz + div - 1) / div;
+
+ PRINTD(("\t\taccepted brgval=%d, totspeed=%d\n", *brgval, *totspeed));
-// Returns the best value of I2BRG to meet desired clock speed of I2C with
-// input parameters (clock speed, filter, and predivider value).
-// It returns computer speed value and the difference between it and desired
-// speed.
-static inline int i2c_roundrate (int hz, int speed, int filter, int modval,
- int *brgval, int *totspeed)
-{
- int moddiv = 1 << (5-(modval & 3)),
- brgdiv,
- div;
-
- brgdiv = hz / (moddiv * speed);
-
- *brgval = brgdiv / 2 - 3 - 2*filter ;
-
- if ((*brgval < 0) || (*brgval > 255))
- return -1 ;
-
- brgdiv = 2 * (*brgval + 3 + 2 * filter) ;
- div = moddiv * brgdiv ;
- *totspeed = hz / div ;
-
return 0;
}
-// Sets the I2C clock predivider and divider to meet required clock speed
-static int i2c_setrate (int hz, int speed)
+/*
+ * Sets the I2C clock predivider and divider to meet required clock speed.
+ */
+static int
+i2c_setrate(int hz, int speed)
{
immap_t *immap = (immap_t *)CFG_IMMR ;
- i2c8xx_t *i2c = (i2c8xx_t *)&immap->im_i2c;
+ volatile i2c8xx_t *i2c = (i2c8xx_t *)&immap->im_i2c;
int brgval,
- modval, // 0-3
- bestspeed_diff = speed,
- bestspeed_brgval=0,
- bestspeed_modval=0,
- bestspeed_filter=0,
- totspeed,
- filter=0; // Use this fixed value 'cause the filter has a bug!
-
-#if 0
- for (filter = 0; filter < 2; filter++)
-#endif
+ modval, /* 0-3 */
+ bestspeed_diff = speed,
+ bestspeed_brgval=0,
+ bestspeed_modval=0,
+ bestspeed_filter=0,
+ totspeed,
+ filter = 0; /* Use this fixed value */
+
for (modval = 0; modval < 4; modval++)
- if (i2c_roundrate ( hz, speed,
- filter, modval,
- &brgval, &totspeed) == 0)
- {
- int diff = speed - totspeed ;
-
- if ((diff >= 0) && (diff < bestspeed_diff))
+ {
+ if (i2c_roundrate (hz, speed, filter, modval, &brgval, &totspeed) == 0)
{
- bestspeed_diff = diff ;
- bestspeed_modval = modval;
- bestspeed_brgval = brgval;
- bestspeed_filter = filter;
+ int diff = speed - totspeed ;
+
+ if ((diff >= 0) && (diff < bestspeed_diff))
+ {
+ bestspeed_diff = diff ;
+ bestspeed_modval = modval;
+ bestspeed_brgval = brgval;
+ bestspeed_filter = filter;
+ }
}
- }
+ }
+
+ PRINTD(("[I2C] Best is:\n"));
+ PRINTD(("[I2C] CPU=%dhz RATE=%d F=%d I2MOD=%08x I2BRG=%08x DIFF=%dhz\n",
+ hz, speed,
+ bestspeed_filter, bestspeed_modval, bestspeed_brgval,
+ bestspeed_diff));
- i2c->i2c_i2mod |= ((bestspeed_modval & 3) << 1) | (bestspeed_filter << 3);
+ i2c->i2c_i2mod |= ((bestspeed_modval & 3) << 1) | (bestspeed_filter << 3);
i2c->i2c_i2brg = bestspeed_brgval & 0xff;
-
-#ifdef CONFIG_I2C_DEBUG
- printf("i2mod=%08x i2brg=%08x\n", i2c->i2c_i2mod, i2c->i2c_i2brg);
-#endif
-
+
+ PRINTD(("[I2C] i2mod=%08x i2brg=%08x\n", i2c->i2c_i2mod, i2c->i2c_i2brg));
+
return 1 ;
}
-int i2c_setspeed (int speed)
+void
+i2c_init(int speed, int slaveaddr)
{
- init_data_t *idata = (init_data_t *)(CFG_INIT_RAM_ADDR + CFG_INIT_DATA_OFFSET);
+ init_data_t *idata = (init_data_t *)(CFG_INIT_RAM_ADDR + CFG_INIT_DATA_OFFSET);
+ volatile immap_t *immap = (immap_t *)CFG_IMMR ;
+ volatile cpm8xx_t *cp = (cpm8xx_t *)&immap->im_cpm;
+ volatile i2c8xx_t *i2c = (i2c8xx_t *)&immap->im_i2c;
+ volatile iic_t *iip = (iic_t *)&cp->cp_dparam[PROFF_IIC];
+ ulong rbase, tbase;
+ volatile I2C_BD *rxbd, *txbd;
+ uint dpaddr;
- // Set the I2C BRG Clock division factor from desired i2c rate
- // and current CPU rate (we assume sccr dfbgr field is 0;
- // divide BRGCLK by 1)
+#ifdef CFG_ALLOC_DPRAM
+ dpaddr = iip->iic_rbase;
+ if (dpaddr == 0) {
+ /* need to allocate dual port ram */
+ dpaddr = dpram_alloc_align(
+ (NUM_RX_BDS * sizeof(I2C_BD)) + (NUM_TX_BDS * sizeof(I2C_BD)) +
+ MAX_TX_SPACE, 8);
+ }
+#else
+ dpaddr = CPM_I2C_BASE;
+#endif
- debug("\n[I2C ] Setting rate...");
+ /*
+ * initialise data in dual port ram:
+ *
+ * dpaddr->rbase -> rx BD (NUM_RX_BDS * sizeof(I2C_BD) bytes)
+ * tbase -> tx BD (NUM_TX_BDS * sizeof(I2C_BD) bytes)
+ * tx buffer (MAX_TX_SPACE bytes)
+ */
+
+ rbase = dpaddr;
+ tbase = rbase + NUM_RX_BDS * sizeof(I2C_BD);
+
+ /* Disable relocation */
+ iip->iic_rpbase = 0 ;
+
+ /* Initialize Port B I2C pins. */
+ cp->cp_pbpar |= 0x00000030;
+ cp->cp_pbdir |= 0x00000030;
+ cp->cp_pbodr |= 0x00000030;
+
+ /* Disable interrupts */
+ i2c->i2c_i2mod = 0x00;
+ i2c->i2c_i2cmr = 0x00;
+ i2c->i2c_i2cer = 0xff;
+ i2c->i2c_i2add = slaveaddr;
+
+ /*
+ * Set the I2C BRG Clock division factor from desired i2c rate
+ * and current CPU rate (we assume sccr dfbgr field is 0;
+ * divide BRGCLK by 1)
+ */
+ PRINTD(("[I2C] Setting rate...\n"));
+ i2c_setrate (idata->cpu_clk, speed) ;
+
+ /* Set I2C controller in master mode */
+ i2c->i2c_i2com = 0x01;
- i2c_setrate (idata->cpu_clk , speed) ;
-
- return ERROR_I2C_NONE ;
-}
+ /* Set SDMA bus arbitration level to 5 (SDCR) */
+ immap->im_siu_conf.sc_sdcr = 0x0001 ;
-int i2c_init(void)
-{
- immap_t *immap = (immap_t *)CFG_IMMR ;
- volatile cpm8xx_t *cp;
-
- /* Get pointer to Communication Processor
- * and to internal registers
- */
- cp = (cpm8xx_t *)&immap->im_cpm ;
- iip = (iic_t *)&cp->cp_dparam[PROFF_IIC];
- i2c = (i2c8xx_t *)&(immap->im_i2c);
-
- // Disable relocation
- iip->iic_rpbase = 0 ;
-
- /* Initialize Port B I2C pins. */
- cp->cp_pbpar |= 0x00000030;
- cp->cp_pbdir |= 0x00000030;
- cp->cp_pbodr |= 0x00000030;
+ /* Initialize Tx/Rx parameters */
+ iip->iic_rbase = rbase;
+ iip->iic_tbase = tbase;
+ rxbd = (I2C_BD *)((unsigned char *)&cp->cp_dpmem[iip->iic_rbase]);
+ txbd = (I2C_BD *)((unsigned char *)&cp->cp_dpmem[iip->iic_tbase]);
- /* Disable interrupts. */
- i2c->i2c_i2mod = 0;
- i2c->i2c_i2cmr = 0;
- i2c->i2c_i2cer = 0xff;
+ PRINTD(("[I2C] rbase = %04x\n", iip->iic_rbase));
+ PRINTD(("[I2C] tbase = %04x\n", iip->iic_tbase));
+ PRINTD(("[I2C] rxbd = %08x\n", (int)rxbd));
+ PRINTD(("[I2C] txbd = %08x\n", (int)txbd));
- /* Set I2C controller in master mode */
- i2c->i2c_i2com = 0x01;
+ /* Set big endian byte order */
+ iip->iic_tfcr = 0x10;
+ iip->iic_rfcr = 0x10;
- // Set SDMA bus arbitration level to 5 (SDCR)
- immap->im_siu_conf.sc_sdcr = 0x0001 ;
+ /* Set maximum receive size. */
+ iip->iic_mrblr = I2C_RXTX_LEN;
+
+ cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_I2C, CPM_CR_INIT_TRX) | CPM_CR_FLG;
+ do {
+ __asm__ __volatile__ ("eieio");
+ } while (cp->cp_cpcr & CPM_CR_FLG);
-#ifdef CFG_ALLOC_DPRAM
- /* Initialize Tx/Rx parameters.*/
- iip->iic_rbptr = iip->iic_rbase = dpram_alloc_align(sizeof(cbd_t),8) ;
- iip->iic_tbptr = iip->iic_tbase = dpram_alloc_align(sizeof(cbd_t),8) ;
+ /* Clear events and interrupts */
+ i2c->i2c_i2cer = 0xff;
+ i2c->i2c_i2cmr = 0x00;
+}
- rxbd = (cbd_t *)((unsigned char *)&cp->cp_dpmem[iip->iic_rbase]);
- txbd = (cbd_t *)((unsigned char *)&cp->cp_dpmem[iip->iic_tbase]);
+void
+i2c_newio(i2c_state_t *state)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR ;
+ volatile cpm8xx_t *cp = (cpm8xx_t *)&immap->im_cpm;
+ volatile iic_t *iip = (iic_t *)&cp->cp_dparam[PROFF_IIC];
- // Alloc rx and tx buffers into DPRAM
- rxbuf = (unsigned char *)&cp->cp_dpmem[dpram_alloc(I2C_RX_LEN)] ;
- txbuf = (unsigned char *)&cp->cp_dpmem[dpram_alloc(I2C_TX_LEN)] ;
-#else
- {
- ulong base = CPM_I2C_BASE ;
+ PRINTD(("[I2C] i2c_newio\n"));
- /* Initialize Tx/Rx parameters.*/
- iip->iic_rbptr = iip->iic_rbase = base ; base += sizeof(cbd_t) ;
- iip->iic_tbptr = iip->iic_tbase = base ; base += sizeof(cbd_t) ;
+ state->rx_idx = 0;
+ state->tx_idx = 0;
+ state->rxbd = (void*)&cp->cp_dpmem[iip->iic_rbase];
+ state->txbd = (void*)&cp->cp_dpmem[iip->iic_tbase];
+ state->tx_space = MAX_TX_SPACE;
+ state->tx_buf = (uchar*)state->txbd + NUM_TX_BDS * sizeof(I2C_BD);
+
+ PRINTD(("[I2C] rxbd = %08x\n", (int)state->rxbd));
+ PRINTD(("[I2C] txbd = %08x\n", (int)state->txbd));
+ PRINTD(("[I2C] tx_buf = %08x\n", (int)state->tx_buf));
+
+ /* clear the buffer memory */
+ memset((char *)state->tx_buf, 0, MAX_TX_SPACE);
+}
- rxbd = (cbd_t *)((unsigned char *)&cp->cp_dpmem[iip->iic_rbase]);
- txbd = (cbd_t *)((unsigned char *)&cp->cp_dpmem[iip->iic_tbase]);
- }
-#endif
+int
+i2c_send(i2c_state_t *state,
+ unsigned char address,
+ unsigned char secondary_address,
+ unsigned int flags,
+ unsigned short size,
+ unsigned char *dataout)
+{
+ volatile I2C_BD *txbd;
+ int i,j;
-#ifdef CONFIG_I2C_DEBUG
- printf("Rxbd = %08x\n", (int)rxbd);
- printf("Txbd = %08x\n", (int)txbd);
- printf("Rxbuf = %08x (%d)\n", (int)rxbuf, I2C_RX_LEN);
- printf("Txbuf = %08x (%d)\n", (int)txbuf, I2C_TX_LEN);
-#endif
+ PRINTD(("[I2C] i2c_send add=%02d sec=%02d flag=%02d size=%d\n",
+ address, secondary_address, flags, size));
+
+ /* trying to send message larger than BD */
+ if (size > I2C_RXTX_LEN)
+ return I2CERR_MSG_TOO_LONG;
- cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_I2C, CPM_CR_INIT_TRX) | CPM_CR_FLG;
- while (cp->cp_cpcr & CPM_CR_FLG);
+ /* no more free bds */
+ if (state->tx_idx >= NUM_TX_BDS || state->tx_space < (2 + size))
+ return I2CERR_NO_BUFFERS;
+
+ txbd = (I2C_BD *)state->txbd;
+ txbd->addr = state->tx_buf;
+
+ PRINTD(("[I2C] txbd = %08x\n", (int)txbd));
+
+ PRINTD(("[I2C] Formatting addresses...\n"));
+ if (flags & I2CF_ENABLE_SECONDARY)
+ {
+ txbd->length = size + 2; /* Length of message plus dest addresses */
+ txbd->addr[0] = address << 1;
+ txbd->addr[1] = secondary_address;
+ i = 2;
+ }
+ else
+ {
+ txbd->length = size + 1; /* Length of message plus dest address */
+ txbd->addr[0] = address << 1; /* Write destination address to BD */
+ i = 1;
+ }
+
+ /* set up txbd */
+ txbd->status = BD_SC_READY;
+ if (flags & I2CF_START_COND)
+ txbd->status |= BD_I2C_TX_START;
+ if (flags & I2CF_STOP_COND)
+ txbd->status |= BD_SC_LAST | BD_SC_WRAP;
+
+ /* Copy data to send into buffer */
+ PRINTD(("[I2C] copy data...\n"));
+ for(j = 0; j < size; i++, j++)
+ txbd->addr[i] = dataout[j];
+
+ PRINTD(("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
+ txbd->length,
+ txbd->status,
+ txbd->addr[0],
+ txbd->addr[1]));
+
+ /* advance state */
+ state->tx_buf += txbd->length;
+ state->tx_space -= txbd->length;
+ state->tx_idx++;
+ state->txbd = (void*)(txbd + 1);
+
+ return 0;
+}
- /* Set big endian byte order */
- iip->iic_tfcr = 0x15;
- iip->iic_rfcr = 0x15;
+int i2c_receive(i2c_state_t *state,
+ unsigned char address,
+ unsigned char secondary_address,
+ unsigned int flags,
+ unsigned short size_to_expect,
+ unsigned char *datain)
+{
+ volatile I2C_BD *rxbd, *txbd;
- /* Set maximum receive size. */
- iip->iic_mrblr = I2C_RX_LEN;
+ PRINTD(("[I2C] i2c_receive %02d %02d %02d\n", address, secondary_address, flags));
- debug("\n[I2C ] Clearing the buffer memory...");
+ /* Expected to receive too much */
+ if (size_to_expect > I2C_RXTX_LEN)
+ return I2CERR_MSG_TOO_LONG;
+
+ /* no more free bds */
+ if (state->tx_idx >= NUM_TX_BDS || state->rx_idx >= NUM_RX_BDS
+ || state->tx_space < 2)
+ return I2CERR_NO_BUFFERS;
- // Clear the buffer memory
- memset ((char *)rxbuf, I2C_RX_LEN, 0);
- memset ((char *)txbuf, I2C_TX_LEN, 0);
-
- debug("\n[I2C ] Initializing BD's...");
+ rxbd = (I2C_BD *)state->rxbd;
+ txbd = (I2C_BD *)state->txbd;
- // Initialize the BD's
-
- // Rx: Wrap, no interrupt, empty
- rxbd->cbd_bufaddr = (ulong)rxbuf;
- rxbd->cbd_sc = 0xa800;
+ PRINTD(("[I2C] rxbd = %08x\n", (int)rxbd));
+ PRINTD(("[I2C] txbd = %08x\n", (int)txbd));
- // Tx: Wrap, no interrupt, not ready to send, last
- txbd->cbd_bufaddr = (ulong)txbuf;
- txbd->cbd_sc = 0x2800;
+ txbd->addr = state->tx_buf;
- // Clear events and interrupts
- i2c->i2c_i2cer = 0xff ;
- i2c->i2c_i2cmr = 0 ;
-
- return ERROR_I2C_NONE ;
-}
-
-int i2c_send( unsigned char address,
- unsigned char secondary_address,
- int enable_secondary,
- unsigned short size, unsigned char dataout[] )
-{
- unsigned char *buffer = (unsigned char *)txbd->cbd_bufaddr ;
- int i,j;
-
- if( size > I2C_TX_LEN ) /* Trying to send message larger than BD */
- return ERROR_I2C_LENGTH;
-
- debug("\n[I2C ] Waiting for transmit buffer empty...");
- while( txbd->cbd_sc & TXBD_R ) ; // Loop until previous data sent
-
- debug("\n[I2C ] Formatting addresses...");
- if( enable_secondary ) /* Device has an internal address */
- {
- txbd->cbd_datlen = size + 2; /* Length of message plus dest addresses */
- buffer[0] = address;
- buffer[0] &= ~(0x01);
- buffer[1] = secondary_address;
- i = 2;
- }
+ /* set up TXBD for destination address */
+ if (flags & I2CF_ENABLE_SECONDARY)
+ {
+ txbd->length = 2;
+ txbd->addr[0] = address << 1; /* Write data */
+ txbd->addr[1] = secondary_address; /* Internal address */
+ txbd->status = BD_SC_READY;
+ }
else
- {
- txbd->cbd_datlen = size + 1; /* Length of message plus dest address */
- buffer[0] = address; /* Write destination address to BD */
- buffer[0] &= ~(0x01); /* Set address to write */
- i = 1;
- }
-
-#ifdef CONFIG_I2C_DEBUG
- printf("Length = %d addr[0] = %08x addr[1] = %08x\n",
- txbd->cbd_datlen,
- buffer[0],
- buffer[1]);
-#endif
-
- /* Copy data to send into buffer */
- debug("\n[I2C ] Copying data into buffer...");
- for( j = 0; j < size; i++, j++ )
- buffer[ i ] = dataout[j];
-
- /* Ready to Transmit, wrap, last */
- debug("\n[I2C ] Waiting to transmit...");
- txbd->cbd_sc = txbd->cbd_sc | TXBD_R | TXBD_W | TXBD_L | TXBD_S ;
-
- /* Enable I2C */
- debug("\n[I2C ] Enabling I2C...");
- i2c->i2c_i2mod |= 1;
-
- /* Transmit */
- debug("\n[I2C ] Transmitting...");
- i2c->i2c_i2com |= 0x80;
-
- debug("\n[I2C ] Waiting for transmit buffer empty...");
- udelay (DELAY_US) ; // Why without this it doesnt work?
- while( txbd->cbd_sc & TXBD_R );
-
- /* Turn off I2C */
- debug("\n[I2C ] Turning off I2C...");
- i2c->i2c_i2mod &= (~1);
-
- return ERROR_I2C_NONE ;
+ {
+ txbd->length = 1 + size_to_expect;
+ txbd->addr[0] = (address << 1) | 0x01;
+ txbd->status = BD_SC_READY;
+ memset(&txbd->addr[1], 0, txbd->length);
+ }
+
+ /* set up rxbd for reception */
+ rxbd->status = BD_SC_EMPTY;
+ rxbd->length = size_to_expect;
+ rxbd->addr = datain;
+
+ if (flags & I2CF_START_COND)
+ txbd->status |= BD_I2C_TX_START;
+ if (flags & I2CF_STOP_COND)
+ {
+ txbd->status |= BD_SC_LAST | BD_SC_WRAP;
+ rxbd->status |= BD_SC_WRAP;
+ }
+
+ PRINTD(("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
+ txbd->length,
+ txbd->status,
+ txbd->addr[0],
+ txbd->addr[1]));
+ PRINTD(("[I2C] rxbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
+ rxbd->length,
+ rxbd->status,
+ rxbd->addr[0],
+ rxbd->addr[1]));
+
+ /* advance state */
+ state->tx_buf += txbd->length;
+ state->tx_space -= txbd->length;
+ state->tx_idx++;
+ state->txbd = (void*)(txbd + 1);
+ state->rx_idx++;
+ state->rxbd = (void*)(rxbd + 1);
+
+ return 0;
}
-int i2c_receive(unsigned char address,
- unsigned char secondary_address,
- int enable_secondary,
- unsigned short size_to_expect, unsigned char datain[] )
+
+int i2c_doio(i2c_state_t *state)
{
- unsigned char *buffer = (unsigned char *)txbd->cbd_bufaddr ;
- int i, j;
-
- if( size_to_expect > I2C_RX_LEN )
- return ERROR_I2C_LENGTH; /* Expected to receive too much */
-
- /* Turn on I2C */
- i2c->i2c_i2mod |= 0x01;
-
- /* Setup TXBD for destination address */
- if( enable_secondary )
- {
- txbd->cbd_datlen = 2;
- buffer[0] = address | 0x00; /* Write data */
- buffer[1] = secondary_address; /* Internal address */
- txbd->cbd_sc = TXBD_R;
-
- /* Reset the rxbd */
- rxbd->cbd_sc = RXBD_E | RXBD_W;
-
- /* Begin transmission */
- i2c->i2c_i2com |= 0x80;
- }
- else
- {
- txbd->cbd_datlen = 1 + size_to_expect;
- buffer[0] = address | 0x01;
-
- /* Buffer ready to transmit, wrap, loop */
- txbd->cbd_sc |= TXBD_R | TXBD_W | TXBD_L;
-
- /* Reset the rxbd */
- rxbd->cbd_sc = RXBD_E | RXBD_W;
-
+ volatile immap_t *immap = (immap_t *)CFG_IMMR ;
+ volatile cpm8xx_t *cp = (cpm8xx_t *)&immap->im_cpm;
+ volatile iic_t *iip = (iic_t *)&cp->cp_dparam[PROFF_IIC];
+ volatile i2c8xx_t *i2c = (i2c8xx_t *)&immap->im_i2c;
+ volatile I2C_BD *txbd, *rxbd;
+ volatile int j = 0;
+
+ PRINTD(("[I2C] i2c_doio\n"));
+
+ if (state->tx_idx <= 0 && state->rx_idx <= 0) {
+ PRINTD(("[I2C] No I/O is queued\n"));
+ return I2CERR_QUEUE_EMPTY;
+ }
+
+ iip->iic_rbptr = iip->iic_rbase;
+ iip->iic_tbptr = iip->iic_tbase;
+
+ /* Enable I2C */
+ PRINTD(("[I2C] Enabling I2C...\n"));
+ i2c->i2c_i2mod |= 0x01;
+
/* Begin transmission */
i2c->i2c_i2com |= 0x80;
-
- while( txbd->cbd_sc & TXBD_R); /* Loop until transmit completed */
- }
-
- while( rxbd->cbd_sc & RXBD_E); /* Wait until receive is finished */
-
- for( i= 0, j = 0; j < size_to_expect; j++, i++ ) /* Copy data to datain[] */
- datain[j] = buffer[i];
-
- /* Turn off I2C */
- i2c->i2c_i2mod &= (~1);
-
- return ERROR_I2C_NONE ;
+
+ /* This is a patch! */
+ udelay (DELAY_US)
+ ;
+
+ /* Loop until transmit & receive completed */
+
+ if (state->tx_idx > 0) {
+ txbd = ((I2C_BD*)state->txbd) - 1;
+ PRINTD(("[I2C] Transmitting...(txbd=0x%08lx)\n", (ulong)txbd));
+ while((txbd->status & BD_SC_READY) && (j++ < TOUT_LOOP)) {
+ if (tstc()) {
+ switch (getc()) {
+ case '\0':
+ case 0x03: /* ^C - Control C */
+ return (-1);
+ }
+ }
+ __asm__ __volatile__ ("eieio");
+ }
+ }
+
+ if ((state->rx_idx > 0) && (j < TOUT_LOOP)) {
+ rxbd = ((I2C_BD*)state->rxbd) - 1;
+ PRINTD(("[I2C] Receiving...(rxbd=0x%08lx)\n", (ulong)rxbd));
+ while((rxbd->status & BD_SC_EMPTY) && (j++ < TOUT_LOOP)) {
+ if (tstc()) {
+ switch (getc()) {
+ case '\0':
+ case 0x03: /* ^C - Control C */
+ return (-1);
+ }
+ }
+ __asm__ __volatile__ ("eieio");
+ }
+ }
+
+ /* Turn off I2C */
+ i2c->i2c_i2mod &= ~0x01;
+
+ return (j >= TOUT_LOOP) ? I2CERR_TIMEOUT : 0;
}
-#endif
+
+#endif /* CONFIG_I2C */
| 16-Jan-00 Added support for booting with IP of 0x0 MKW
| 15-Mar-00 Updated enetInit() to enable broadcast addresses in the
| EMAC_RXM register. JWB
+ | 12-Mar-01 anne-sophie.harnois@nextream.fr
+ | - Variables are compatible with those already defined in
+ | include/net.h
+ | - Receive buffer descriptor ring is used to send buffers
+ | to the user
+ | - Info print about send/received/handled packet number if
+ | INFO_405_ENET is set
+-----------------------------------------------------------------------------*/
#include <ppcboot.h>
| the buffers for an PCI ethernet device (if present) would start.
+-----------------------------------------------------------------------------*/
#define NUM_TX_BUFF 1
-#define NUM_RX_BUFF 4
+/* AS.HARNOIS
+ * Use PKTBUFSRX (include/net.h) instead of setting NUM_RX_BUFF again
+ * These both variables are used to define the same thing!
+ * #define NUM_RX_BUFF 4
+ */
+#define NUM_RX_BUFF PKTBUFSRX
+
+
#define TX_BUF_START 0x0000A000
#define RX_BUF_START 0x0000A800
/* Ethernet Transmit and Receive Buffers */
-#define DBUF_LENGTH 1520
-/* #define PKTBUFSRX 2 */
+/* AS.HARNOIS
+ * In the same way ENET_MAX_MTU and ENET_MAX_MTU_ALIGNED are set from
+ * PKTSIZE and PKTSIZE_ALIGN (include/net.h)
+ */
+#define ENET_MAX_MTU PKTSIZE
+#define ENET_MAX_MTU_ALIGNED PKTSIZE_ALIGN
-/* static char rxbuf[PKTBUFSRX][ DBUF_LENGTH ]; */
static char *txbuf_ptr;
/*-----------------------------------------------------------------------------+
static int tx_u_index = 0; /* Transmit User Queue Index */
static int tx_run[NUM_TX_BUFF]; /* Transmit Running Queue */
-static volatile int rx_ptr = -1;
+/* #define INFO_405_ENET 1 */
+#ifdef INFO_405_ENET
+static int packetSent = 0;
+static int packetReceived = 0;
+static int packetHandled = 0;
+#endif
static char emac_hwd_addr[ENET_ADDR_LENGTH];
msr = get_msr();
set_msr(msr & ~(MSR_EE));
+#ifdef INFO_405_ENET
+ /* AS.HARNOIS
+ * We should have :
+ * packetHandled <= packetReceived <= packetHandled+PKTBUFSRX
+ * In the most cases packetHandled = packetReceived, but it is
+ * possible that new packets (without relationship with current transfer)
+ * have got the time to arrived before netloop calls eth_halt
+ */
+ printf ("About preceeding transfer:\n- Sent packet number %d\n- Received packet number %d\n- Handled packet number %d\n",
+ packetSent, packetReceived, packetHandled);
+ packetSent = 0;
+ packetReceived = 0;
+ packetHandled = 0;
+#endif
+
/* MAL RESET */
mtdcr(malmcr, MAL_CR_MMSR);
tx[i].ctrl = 0;
tx[i].data_len = 0;
if (first_init == 0)
- txbuf_ptr = (char *)malloc(DBUF_LENGTH);
+ txbuf_ptr = (char *)malloc(ENET_MAX_MTU_ALIGNED);
tx[i].data_ptr = txbuf_ptr;
if ((NUM_TX_BUFF - 1) == i)
tx[i].ctrl |= MAL_TX_CTRL_WRAP;
ulong time_start, time_now;
unsigned long temp_txm0;
-
ef_ptr = (struct enet_frame *) ptr;
/*-----------------------------------------------------------------------+
tx[tx_slot].ctrl |= MAL_TX_CTRL_READY;
out32 (EMAC_TXM0, in32 (EMAC_TXM0) | EMAC_TXM0_GNP0);
+#ifdef INFO_405_ENET
+ packetSent++;
+#endif
/*-----------------------------------------------------------------------+
| poll unitl the packet is sent and then make sure it is OK
unsigned long mal_errr)
{
mtdcr(malesr, isr); /* clear interrupt */
- printf ("MAL error occured.... ISR = %lx UIC = = %lx MAL_DEF = %lx MAL_ERR= %lx \n",
+
+ /* clear DE interrupt */
+ mtdcr(maltxdeir,0xC0000000);
+ mtdcr(malrxdeir,0x80000000);
+
+
+ printf ("\nMAL error occured.... ISR = %lx UIC = = %lx MAL_DEF = %lx MAL_ERR= %lx \n",
isr, uic, maldef, mal_errr);
#if 0
eth_init(NULL);
#endif
- mtdcr(malrxcarr, 0x80000000);
- mtdcr(malrxcarr, 0x00000000);
- mtdcr(malrxcasr, 0x80000000);
-
- mtdcr(maltxcarr, 0x80000000); /* 2 channels */
- mtdcr(maltxcarr, 0x00000000);
- mtdcr(maltxcasr, 0x80000000); /* 1 channel */
+ eth_halt();
}
/*-----------------------------------------------------------------------------+
int handled=0;
int i;
+ int loop_count=0;
rx_eob_isr = mfdcr(malrxeobisr);
if ((0x80000000 >>( EMAC_RXCHL-1)) & rx_eob_isr)
{ /* do all */
i = rx_slot;
- if (MAL_RX_CTRL_EMPTY & rx[i].ctrl)
+ if ((MAL_RX_CTRL_EMPTY & rx[i].ctrl) || (loop_count >= NUM_RX_BUFF))
break;
+ loop_count ++;
rx_slot++;
if (NUM_RX_BUFF == rx_slot)
rx_slot = 0;
stats.emac.data_len_err++; /* Error at Rx */
} /* !data_len */
- else
+
+ /* AS.HARNOIS */
+ /* Check if user has already eaten buffer */
+ /* if not => ERROR */
+ else if (rx_ready[rx_i_index] != -1)
{
+ printf("ERROR : Receive buffers are full!\n");
+ break;
+ }
+
+ else
+ {
stats.emac.rx_frames++;
stats.emac.rx += data_len;
ef_ptr = (struct enet_frame *) rx[i].data_ptr;
-
- /*
- * Set rx pointer
- */
- rx_ptr = i;
-
+#ifdef INFO_405_ENET
+ packetReceived++;
+#endif
+ /* AS.HARNOIS
+ * use ring buffer
+ */
+ rx_ready[rx_i_index] = i;
+ rx_i_index++;
+ if (NUM_RX_BUFF == rx_i_index)
+ rx_i_index = 0;
+
// printf("X"); /* test-only */
- rx[i].ctrl |= MAL_RX_CTRL_EMPTY; /* Free Recv Buffer */
-
+ /* AS.HARNOIS
+ * free receive buffer only when
+ * buffer has been handled (eth_rx)
+ rx[i].ctrl |= MAL_RX_CTRL_EMPTY;
+ */
} /* if data_len */
} /* while */
} /* if EMACK_RXCHL */
int eth_rx(void)
{
int length;
- int i;
+ int user_index;
unsigned long msr;
for (;;)
{
- if (rx_ptr == -1)
+ /* AS.HARNOIS
+ * use ring buffer and
+ * get index from rx buffer desciptor queue
+ */
+ user_index = rx_ready[rx_u_index];
+ if (user_index == -1)
{
length = -1;
break; /* nothing received - leave for() loop */
msr = get_msr();
set_msr(msr & ~(MSR_EE));
- i = rx_ptr;
- length = rx[i].data_len;
+ length = rx[user_index].data_len;
/* Pass the packet up to the protocol layers. */
// NetReceive(NetRxPackets[rxIdx], length - 4);
// NetReceive(NetRxPackets[i], length);
- NetReceive(NetRxPackets[i], length - 4);
-
- rx_ptr = -1;
-
+ NetReceive(NetRxPackets[user_index], length - 4);
+ /* Free Recv Buffer */
+ rx[user_index].ctrl |= MAL_RX_CTRL_EMPTY;
+ /* Free rx buffer descriptor queue */
+ rx_ready[rx_u_index] = -1;
+ rx_u_index++;
+ if (NUM_RX_BUFF == rx_u_index)
+ rx_u_index = 0;
+
+#ifdef INFO_405_ENET
+ packetHandled++;
+#endif
+
set_msr(msr); /* Enable IRQ's */
}
return length;
| General enternet defines. 802 frames are not supported.
+-----------------------------------------------------------------------------*/
#define ENET_ADDR_LENGTH 6
-#define ENET_MAX_MTU 1518
-#define ENET_MAX_MTU_ALIGNED 1536
#define ENET_ARPTYPE 0x806
#define ARP_REQUEST 1
#define ARP_REPLY 2
unsigned long nsec;
};
-struct memblock {
- char data[ENET_MAX_MTU_ALIGNED]; /* room for max packet */
-};
-
/*Register addresses */
#define EMAC_BASE 0xEF600800
#define CMD_TBL_SIUINFO
#define CMD_TBL_MEMCINFO
#define CMD_TBL_SITINFO
+#ifdef CONFIG_8260
#define CMD_TBL_ICINFO
+#endif
#define CMD_TBL_CARINFO
#define CMD_TBL_IOPINFO
#define CMD_TBL_DMAINFO
#define SICR_ENET_CLKRT ((uint)0x0000002C)
#endif /* CONFIG_IP860 */
+/*** LWMON **********************************************************/
+
+#if defined(CONFIG_LWMON)
+/* Bits in parallel I/O port registers that have to be set/cleared
+ * to configure the pins for SCC2 use.
+ */
+#define PROFF_ENET PROFF_SCC2
+#define CPM_CR_ENET CPM_CR_CH_SCC2
+#define SCC_ENET 1
+#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
+#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
+#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */
+#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
+
+#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
+
+#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
+#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
+
+/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
+ * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
+ */
+#define SICR_ENET_MASK ((uint)0x0000ff00)
+#define SICR_ENET_CLKRT ((uint)0x00002600)
+#endif /* CONFIG_LWMON */
+
/*** SXNI855T ******************************************************/
#if defined(CONFIG_SXNI855T)
#endif /* CONFIG_SXNI855T */
+/*** GTH ******************************************************/
+
+#ifdef CONFIG_GTH
+#ifdef CONFIG_FEC_ENET
+#define FEC_ENET /* use FEC for EThernet */
+#endif /* CONFIG_FEC_ETHERNET */
+
+/* This ENET stuff is for GTH 10 Mbit ( SCC ) */
+#define PROFF_ENET PROFF_SCC1
+#define CPM_CR_ENET CPM_CR_CH_SCC1
+#define SCC_ENET 0
+
+#define PA_ENET_RXD ((ushort)0x0001) /* PA15 */
+#define PA_ENET_TXD ((ushort)0x0002) /* PA14 */
+#define PA_ENET_TCLK ((ushort)0x0800) /* PA4 */
+#define PA_ENET_RCLK ((ushort)0x0400) /* PA5 */
+
+#define PB_ENET_TENA ((uint)0x00001000) /* PB19 */
+
+#define PC_ENET_CLSN ((ushort)0x0010) /* PC11 */
+#define PC_ENET_RENA ((ushort)0x0020) /* PC10 */
+
+/* NOTE. This is reset for 10Mbit port only */
+#define PC_ENET_RESET ((ushort)0x0100) /* PC 7 */
+
+#define SICR_ENET_MASK ((uint)0x000000ff)
+
+/* TCLK PA4 -->CLK4, RCLK PA5 -->CLK3 */
+#define SICR_ENET_CLKRT ((uint)0x00000037)
+
+#endif /* CONFIG_GTH */
+
/*********************************************************************/
/* SCC Event register as used by Ethernet.
--- /dev/null
+/*
+ * Parameters for GTH board
+ * Based on FADS860T
+ * by thomas.lange@corelatus.com
+
+ * A collection of structures, addresses, and values associated with
+ * the Motorola 860T FADS board. Copied from the MBX stuff.
+ * Magnus Damm added defines for 8xxrom and extended bd_info.
+ * Helmut Buchsbaum added bitvalues for BCSRx
+ *
+ * Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
+ */
+
+/*
+ * ff000000 -> ff00ffff : IMAP internal in the cpu
+ * e0000000 -> ennnnnnn : pcmcia
+ * 98000000 -> 983nnnnn : FPGA 4MB
+ * 90000000 -> 903nnnnn : FPGA 4MB
+ * 80000000 -> 80nnnnnn : flash connected to CS0, final ( real ) location
+ * 00000000 -> nnnnnnnn : sdram
+ */
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#include <mpc8xx_irq.h>
+
+#define CONFIG_MPC860 1
+#define CONFIG_MPC860T 1
+#define CONFIG_GTH 1
+
+#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
+#undef CONFIG_8xx_CONS_SMC2
+#undef CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE 9600
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+
+#define MPC8XX_FACT 3 /* Multiply by 3 */
+#define MPC8XX_XIN 16384000 /* 16.384 MHz */
+#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT))
+#define CFG_CLKS_IN_HZ 1 /* everything, incl board info, in Hz */
+
+#if 0
+#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
+#else
+#define CONFIG_BOOTDELAY 1 /* autoboot after 1 seconds */
+#endif
+
+#define CONFIG_BOOT_RETRY_TIME 30 /* Retry boot in 30 secs */
+
+// Only interrupt boot if space is pressed
+// If a long serial cable is connected but
+// other end is dead, garbage will be read
+#define CONFIG_AUTOBOOT_KEYED 1
+#define CONFIG_AUTOBOOT_PROMPT "Press space to abort autoboot\n"
+#define CONFIG_AUTOBOOT_DELAY_STR " "
+#define CONFIG_AUTOBOOT_STOP_STR "s"
+
+#if 0
+// Net boot
+/* Loads a tftp image and starts it */
+#define CONFIG_BOOTCOMMAND "bootp;bootm 100000" /* autoboot command */
+#define CONFIG_BOOTARGS "panic=1"
+#else
+// Compact flash boot
+#define CONFIG_BOOTARGS "panic=1 root=/dev/hda4"
+#define CONFIG_BOOTCOMMAND "disk 100000 0:2;bootm 100000"
+#endif
+
+#undef CONFIG_WATCHDOG
+// #define CONFIG_WATCHDOG 1 /* watchdog disabled */
+
+/* choose SCC1 ethernet (10BASET on motherboard)
+ * or FEC ethernet (10/100 on daughterboard)
+ */
+#if 1
+#define CONFIG_SCC1_ENET 1 /* use SCC1 ethernet */
+#undef CONFIG_FEC_ENET /* disable FEC ethernet */
+#define CFG_DISCOVER_PHY
+#else
+#undef CONFIG_SCC1_ENET /* disable SCC1 ethernet */
+#define CONFIG_FEC_ENET 1 /* use FEC ethernet */
+#define CFG_DISCOVER_PHY
+#endif
+#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
+#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
+#endif
+
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_IDE)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_PROMPT "=>" /* Monitor Command Prompt */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x0100000 /* memtest works on */
+#define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */
+
+/* Default location to load data from net */
+#define CFG_LOAD_ADDR 0x100000
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR 0xFF000000
+#define CFG_IMMR_SIZE ((uint)(64 * 1024))
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR CFG_IMMR
+#define CFG_INIT_RAM_END 0x3000 /* End of used area in DPRAM */
+#define CFG_INIT_DATA_SIZE 64 /* size in bytes reserved for initial data */
+#define CFG_INIT_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_INIT_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE 0x00000000
+
+#define CFG_FLASH_BASE 0x80000000
+
+#define CFG_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */
+
+#define CFG_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
+
+#ifndef CONFIG_START_IN_RAM
+#define CFG_MONITOR_BASE CFG_FLASH_BASE
+#else
+#define CFG_MONITOR_BASE 0
+#endif
+
+#define CFG_HWINFO_LEN 0x0040 /* Length of HW Info Data */
+#define CFG_MALLOC_LEN (384 << 10) /* Reserve 384 kB for malloc() */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
+
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+#define CFG_ENV_IS_IN_FLASH 1
+#undef CFG_ENV_IS_IN_EEPROM
+#define CFG_ENV_OFFSET 0x00080000
+#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
+
+#define CFG_ENV_SECT_SIZE 0x40000 /* see README - env sector total size */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control 11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+ SYPCR_SWE | SYPCR_SWP)
+#else
+#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration 11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control 11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register 11-27
+ *-----------------------------------------------------------------------
+ */
+
+//FIXME dont use for now
+//#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+//#define CFG_RTCSC (RTCSC_RTF)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control 11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR (PISCR_PS | PISCR_PITF)
+// PITE
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
+ *-----------------------------------------------------------------------
+ * set the PLL, the low-power modes and the reset control (15-29)
+ */
+#define CFG_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \
+ PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register 15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+
+// FIXME check values
+#define SCCR_MASK SCCR_EBDF11
+#define CFG_SCCR (SCCR_TBS|SCCR_RTSEL|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00)
+
+ /*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_DER 0
+
+/* Because of the way the 860 starts up and assigns CS0 the
+* entire address space, we have to set the memory controller
+* differently. Normally, you write the option register
+* first, and then enable the chip select by writing the
+* base register. For CS0, you must write the base register
+* first, followed by the option register.
+*/
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+/* the other CS:s are determined by looking at parameters in BCSRx */
+
+#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
+
+#define CFG_REMAP_OR_AM 0xFF800000 /* 4 MB OR addr mask */
+#define CFG_PRELIM_OR_AM 0xFF800000 /* OR addr mask */
+
+#define FPGA_2_BASE 0x90000000
+#define FPGA_3_BASE 0x98000000
+
+/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */
+#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
+
+#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
+
+
+#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) /* 1 Mbyte until detected and only 1 Mbyte is needed*/
+#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_16 )
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#define CONFIG_ETHADDR DE:AD:BE:EF:00:01 /* Ethernet address */
+
+#ifdef CONFIG_MPC860T
+
+/* Interrupt level assignments.
+*/
+#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */
+
+#endif /* CONFIG_MPC860T */
+
+/* We don't use the 8259.
+*/
+#define NR_8259_INTS 0
+
+/* Machine type
+*/
+#define _MACH_8xx (_MACH_gth)
+
+#ifdef CONFIG_MPC860
+#define PCMCIA_SLOT_A 1
+#define CONFIG_PCMCIA_SLOT_A 1
+#endif
+
+#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
+#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
+#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
+#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
+#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
+#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
+#define CFG_PCMCIA_IO_ADDR (0xEC000000)
+#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
+
+#define CONFIG_IDE_PCCARD 1 /* Use IDE with PC Card Adapter */
+#undef CONFIG_IDE_PCMCIA /* Direct IDE not supported */
+#undef CONFIG_IDE_LED /* LED for ide not supported */
+#undef CONFIG_IDE_RESET /* reset for ide not supported */
+
+#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
+#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
+
+#define CFG_ATA_IDE0_OFFSET 0x0000
+#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
+/* Offset for data I/O */
+#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
+/* Offset for normal register accesses */
+#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+/* Offset for alternate registers */
+#define CFG_ATA_ALT_OFFSET 0x0100
+
+#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ /* Force it - dont measure it */
+
+#define PA_FRONT_LED ((u16)0x4) /* PA 13 */
+
+#define PB_ID_GND ((u32)1) /* PB 31 */
+#define PB_REV_1 ((u32)2) /* PB 30 */
+#define PB_REV_0 ((u32)4) /* PB 29 */
+#define PB_BLUE_LED ((u32)0x400) /* PB 21 */
+#define PB_EEPROM ((u32)0x800) /* PB 20 */
+#define PB_ID_3 ((u32)0x2000) /* PB 18 */
+#define PB_ID_2 ((u32)0x4000) /* PB 17 */
+#define PB_ID_1 ((u32)0x8000) /* PB 16 */
+#define PB_ID_0 ((u32)0x10000) /* PB 15 */
+
+#endif /* __CONFIG_H */
#undef CONFIG_WATCHDOG /* watchdog disabled */
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL & ~(CFG_CMD_ENV))
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL)
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
--- /dev/null
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC823 1 /* This is a MPC823E CPU */
+#define CONFIG_LWMON 1 /* ...on a LWMON board */
+
+#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
+
+#define CONFIG_BAUDRATE 9600
+#if 0
+#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
+#else
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+#endif
+//#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */
+#define CONFIG_BOOTCOMMAND "fli" /* autoboot command */
+
+#define CONFIG_BOOTARGS "root=/dev/nfs rw " \
+ "nfsroot=10.0.0.2:/LinuxPPC " \
+ "nfsaddrs=10.0.0.99:10.0.0.2"
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+#undef CONFIG_STATUS_LED /* Status LED disabled */
+
+#define CONFIG_I2C /* I2C support enabled */
+
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_I2C /*|CFG_CMD_IDE*/)
+
+#define CONFIG_BOOTP_MASK \
+ ((CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) & ~CONFIG_BOOTP_GATEWAY)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*----------------------------------------------------------------------*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
+#define CFG_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */
+
+#define CFG_LOAD_ADDR 0x00100000 /* default load address */
+
+#define CFG_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR 0xFFF00000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR CFG_IMMR
+#define CFG_INIT_RAM_END 0x3000 /* End of used area in DPRAM */
+#define CFG_INIT_DATA_SIZE 64 /* size in bytes reserved for initial data */
+#define CFG_INIT_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_INIT_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_FLASH_BASE 0x40000000
+#ifdef DEBUG
+#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
+#else
+#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
+#endif
+#define CFG_MONITOR_BASE CFG_FLASH_BASE
+#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
+
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+/* XXX Start port with environment in flash; switch to EEPROM later */
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_ADDR 0x407E0000 /* Address of Environment Sector */
+#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment */
+#define CFG_ENV_SECT_SIZE 0x20000 /* we have BIG sectors only :-( */
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control 11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+ SYPCR_SWE | SYPCR_SWP)
+#else
+#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration 11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+/* EARB, DBGC and DBPC are initialised by the HCW */
+/* => 0x000000C0 */
+#define CFG_SIUMCR (SIUMCR_BSC | SIUMCR_GB5E)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control 11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control 11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR (PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit, set PLL multiplication factor !
+ */
+/* 0x00405000 */
+#define CFG_PLPRCR_MF 4 /* (4+1) * 13.2 = 66 MHz Clock */
+#define CFG_PLPRCR \
+ ( (CFG_PLPRCR_MF << PLPRCR_MF_SHIFT) | \
+ PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | \
+ /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \
+ PLPRCR_CSR | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/ \
+ )
+
+#define CONFIG_8xx_GCLK_FREQ ((CFG_PLPRCR_MF+1)*13200000)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register 15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK SCCR_EBDF11
+/* 0x01800000 */
+#define CFG_SCCR (SCCR_COM00 | /*SCCR_TBS|*/ \
+ SCCR_RTDIV | SCCR_RTSEL | \
+ /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \
+SCCR_EBDF01 /**** SCCR_EBDF00 ****/ | SCCR_DFSYNC00 | \
+ SCCR_DFBRG00 | SCCR_DFNL000 | \
+ SCCR_DFNH000 | SCCR_DFLCD100 | \
+ SCCR_DFALCD01)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register 11-27
+ *-----------------------------------------------------------------------
+ */
+/* 0x00C3 => 0x0003 */
+#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+
+/*-----------------------------------------------------------------------
+ * RCCR - RISC Controller Configuration Register 19-4
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RCCR 0x0000
+
+/*-----------------------------------------------------------------------
+ * RMDS - RISC Microcode Development Support Control Register
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RMDS 0
+
+/*-----------------------------------------------------------------------
+ *
+ * Interrupt Levels
+ *-----------------------------------------------------------------------
+ */
+#define CFG_CPM_INTERRUPT 13 /* SIU_LEVEL6 */
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_PCMCIA_MEM_ADDR (0x50000000)
+#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
+#define CFG_PCMCIA_DMA_ADDR (0x54000000)
+#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
+#define CFG_PCMCIA_ATTRB_ADDR (0x58000000)
+#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
+#define CFG_PCMCIA_IO_ADDR (0x5C000000)
+#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff
+ *-----------------------------------------------------------------------
+ */
+
+#define CONFIG_IDE_PCCARD 1 /* Use IDE with PC Card Adapter */
+
+#undef CONFIG_IDE_PCMCIA /* Direct IDE not supported */
+#undef CONFIG_IDE_LED /* LED for ide not supported */
+#undef CONFIG_IDE_RESET /* reset for ide not supported */
+
+#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
+#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
+
+#define CFG_ATA_IDE0_OFFSET 0x0000
+
+#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O */
+#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for normal register accesses */
+#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for alternate registers */
+#define CFG_ATA_ALT_OFFSET 0x0100
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+/*#define CFG_DER 0x2002000F*/
+#define CFG_DER 0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH) - second Flash bank optional
+ */
+
+#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
+#define FLASH_BASE1_PRELIM 0x41000000 /* FLASH bank #0 */
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CFG_REMAP_OR_AM 0xFF000000 /* OR addr mask */
+#define CFG_PRELIM_OR_AM 0xFF000000 /* OR addr mask */
+
+/* FLASH timing: ACS = 00, TRLX = 0, CSNT = 1, SCY = 8, EHTR = 0 */
+#define CFG_OR_TIMING_FLASH (OR_SCY_8_CLK)
+
+#define CFG_OR0_REMAP ( CFG_REMAP_OR_AM | OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
+ CFG_OR_TIMING_FLASH)
+#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | OR_ACS_DIV1 | OR_BI | \
+ CFG_OR_TIMING_FLASH)
+/* 16 bit, bank valid */
+#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V )
+
+#define CFG_OR1_REMAP CFG_OR0_REMAP
+#define CFG_OR1_PRELIM CFG_OR0_PRELIM
+#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V )
+
+/*
+ * BR3/OR3: SDRAM
+ *
+ * Multiplexed addresses, GPL5 output to GPL5_A (don't care)
+ */
+#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank */
+#define SDRAM_PRELIM_OR_AM 0xF0000000 /* map 256 MB (>SDRAM_MAX_SIZE!) */
+#define SDRAM_TIMING OR_SCY_0_CLK /* SDRAM-Timing */
+
+#define SDRAM_MAX_SIZE 0x08000000 /* max 128 MB SDRAM */
+
+#define CFG_OR3_PRELIM (SDRAM_PRELIM_OR_AM | OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING )
+#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+/*
+ * BR5/OR5: Touch Panel
+ *
+ * AM=0xFFC00 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=3 BIH=1 SCY=0 SETA=0 TRLX=0 EHTR=0
+ */
+#define TOUCHPNL_BASE 0x20000000
+#define TOUCHPNL_OR_AM 0xFFFF8000
+#define TOUCHPNL_TIMING OR_SCY_0_CLK
+
+#define CFG_OR5 (TOUCHPNL_OR_AM | OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
+ TOUCHPNL_TIMING )
+#define CFG_BR5 ((TOUCHPNL_BASE & BR_BA_MSK) | BR_PS_32 | BR_V )
+
+/*
+ * Memory Periodic Timer Prescaler
+ */
+
+/* periodic timer for refresh */
+#define CFG_MPTPR 0x200
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+#define CFG_MAMR 0x80802114
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#endif /* __CONFIG_H */
#define INTEL_ID_28F640B3T 0x88988898 /* 64M = 4M x 16 top boot sector */
#define INTEL_ID_28F640B3B 0x88998899 /* 64M = 4M x 16 bottom boot sector */
+#define INTEL_ID_28F320JA3 0x00160016 /* 32M = 128K x 32 */
+#define INTEL_ID_28F640JA3 0x00170017 /* 64M = 128K x 64 */
+#define INTEL_ID_28F128JA3 0x00180018 /* 128M = 128K x 128 */
+
/*-----------------------------------------------------------------------
* Internal FLASH identification codes
*
#define FLASH_INTEL640T 0x003A /* INTEL 28F320B3T ID( 64M = 4M x 16 ) */
#define FLASH_INTEL640B 0x003B /* INTEL 28F320B3B ID( 64M = 4M x 16 ) */
+#define FLASH_28F320JA3 0x003C /* INTEL 28F320JA3 ID( 32M = 128K x 32 */
+#define FLASH_28F640JA3 0x003D /* INTEL 28F640JA3 ID( 64M = 128K x 64 */
+#define FLASH_28F128JA3 0x003E /* INTEL 28F128JA3 ID(128M = 128K x 128 */
+
#define FLASH_28F008S5 0x0050 /* Intel 28F008S5 ( 1M = 64K x 16 ) */
#define FLASH_28F016SV 0x0051 /* Intel 28F016SV (16M = 512k x 16 ) */
#define FLASH_28F800_B 0x0053 /* Intel E28F800B ( 1M = ? ) */
#ifndef _I2C_H_
#define _I2C_H_
-#ifdef CONFIG_MPC8260
+#if defined(CONFIG_CPCI405) || defined(CONFIG_AR405) || defined (CONFIG_WALNUT405)
+
+void i2c_receive(unsigned char address,
+ unsigned short size_to_expect, unsigned char datain[] );
+void i2c_send(unsigned char address,
+ unsigned short size_to_send, unsigned char dataout[] );
+
+#else
#define I2C_RXTX_LEN 128 /* maximum tx/rx buffer length */
#define I2CERR_TIMEOUT 0x03 /* timeout in i2c_doio() */
#define I2CERR_QUEUE_EMPTY 0x04 /* i2c_doio called without send/receive */
-#elif defined(CONFIG_CPCI405) || defined(CONFIG_AR405) || defined (CONFIG_WALNUT405)
-
-void i2c_receive(unsigned char address,
- unsigned short size_to_expect, unsigned char datain[] );
-void i2c_send(unsigned char address,
- unsigned short size_to_send, unsigned char dataout[] );
-
-#else /* !CONFIG_MPC8260 */
-
-
-int i2c_init(void);
-int i2c_send( unsigned char address,
- unsigned char secondary_address,
- int enable_secondary,
- unsigned short size, unsigned char dataout[] );
-int i2c_receive(unsigned char address,
- unsigned char secondary_address,
- int enable_secondary,
- unsigned short size_to_expect, unsigned char datain[] );
-
#endif
#define ERROR_I2C_NONE 0
#define SCCR_DFNH110 0x000000D0 /* Division by 64 (maximum) */
#define SCCR_DFNH111 0x000000E0 /* reserved */
#define SCCR_DFLCD000 0x00000000 /* Division by 1 (default = minimum) */
+#define SCCR_DFLCD001 0x00000004 /* Division by 2 */
+#define SCCR_DFLCD010 0x00000008 /* Division by 4 */
+#define SCCR_DFLCD011 0x0000000C /* Division by 8 */
+#define SCCR_DFLCD100 0x00000010 /* Division by 16 */
#define SCCR_DFLCD101 0x00000014 /* Division by 32 */
#define SCCR_DFLCD110 0x00000018 /* Division by 64 (maximum) */
#define SCCR_DFLCD111 0x0000001C /* reserved */
#define MPTPR_PTP_DIV32 0x0200 /* BRGCLK divided by 32 */
#define MPTPR_PTP_DIV64 0x0100 /* BRGCLK divided by 64 */
+/*-----------------------------------------------------------------------
+ * MCR - Memory Command Register
+ */
+#define MCR_OP_WRITE 0x00000000 /* WRITE command */
+#define MCR_OP_READ 0x40000000 /* READ command */
+#define MCR_OP_RUN 0x80000000 /* RUN command */
+#define MCR_UPM_A 0x00000000 /* Select UPM A */
+#define MCR_UPM_B 0x00800000 /* Select UPM B */
+#define MCR_MB_CS0 0x00000000 /* Use Chip Select /CS0 */
+#define MCR_MB_CS1 0x00020000 /* Use Chip Select /CS1 */
+#define MCR_MB_CS2 0x00040000 /* Use Chip Select /CS2 */
+#define MCR_MB_CS3 0x00060000 /* Use Chip Select /CS3 */
+#define MCR_MB_CS4 0x00080000 /* Use Chip Select /CS4 */
+#define MCR_MB_CS5 0x000A0000 /* Use Chip Select /CS5 */
+#define MCR_MB_CS6 0x000C0000 /* Use Chip Select /CS6 */
+#define MCR_MB_CS7 0x000E0000 /* Use Chip Select /CS7 */
+#define MCR_MLCF(n) (((n)&0xF)<<8) /* Memory Command Loop Count Field */
+#define MCR_MAD(addr) ((addr)&0x3F) /* Memory Array Index */
/*-----------------------------------------------------------------------
* Machine A Mode Register 16-13
* Lets be conservative, and go for 38 * 16. (Must also be
* a multiple of 32 bytes).
*/
-/* #define PKTSIZE 1536 */
-#define PKTSIZE 608
+/*
+ * AS.HARNOIS : Better to set PKTSIZE to maximum size because
+ * traffic type is not always controlled
+ * maximum packet size = 1518
+ * maximum packet size and multiple of 32 bytes = 1536
+ */
+#define PKTSIZE 1518
+#define PKTSIZE_ALIGN 1536
+/*#define PKTSIZE 608*/
/*
* Maximum receive ring size; that is, the number of packets
void pciinfo (int);
#endif
-#if defined(CONFIG_COGENT) || defined(CONFIG_SXNI855T) || defined(CONFIG_RSD_PROTO)
+#if defined(CONFIG_COGENT) || defined(CONFIG_SXNI855T) || \
+ defined(CONFIG_RSD_PROTO) || defined(CONFIG_HYMOD)
/* cogent - $(BOARD)/mb.c */
-/* SXNI855T - $(BOARD)/$(BOARD).c */
+/* SXNI855T and HYMOD - $(BOARD)/$(BOARD).c */
int misc_init_f (void);
void misc_init_r (bd_t *);
#endif
defined(CONFIG_AR405) || \
defined(CONFIG_CANBT) || \
defined(CONFIG_WALNUT405) || \
- defined (CONFIG_CPCIISER4)
+ defined(CONFIG_CPCIISER4) || \
+ defined(CONFIG_ADCIOP)
/* $(BOARD)/$(BOARD).c */
int board_pre_init (void);
#endif
+#if defined(CONFIG_HYMOD)
+void board_postclk_init(void); /* after clocks/timebase, before env/serial */
+#endif
/* $(CPU)/serial.c */
void serial_init (ulong, int);
void console_init_r(ulong); /* After relocation; uses the console stuff */
int console_assign (int file, char *devname); /* Assign the console */
int ctrlc (void);
+int had_ctrlc (void); /* have we had a Control-C since last clear? */
+void clear_ctrlc (void); /* clear the Control-C condition */
/*
* STDIO based functions (can always be used)
#ifndef __VERSION_H__
#define __VERSION_H__
-#define PPCBOOT_VERSION "ppcboot 0.8.3"
+#define PPCBOOT_VERSION "ppcboot 0.9.0-pre1"
#endif /* __VERSION_H__ */
char BootFile[128]; /* Boot File name */
-volatile uchar PktBuf[(PKTBUFSRX+1) * PKTSIZE + PKTALIGN];
+volatile uchar PktBuf[(PKTBUFSRX+1) * PKTSIZE_ALIGN + PKTALIGN];
volatile uchar *NetRxPackets[PKTBUFSRX]; /* Receive packets */
NetTxPacket = &PktBuf[0] + (PKTALIGN - 1);
NetTxPacket -= (ulong)NetTxPacket % PKTALIGN;
for (i = 0; i < PKTBUFSRX; i++) {
- NetRxPackets[i] = NetTxPacket + (i+1)*PKTSIZE;
+ NetRxPackets[i] = NetTxPacket + (i+1)*PKTSIZE_ALIGN;
}
}
* Abort if ctrl-c was pressed.
*/
if (ctrlc()) {
+ eth_halt();
printf("\nAbort\n");
return 0;
}
write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA. */
-#include <stdlib.h>
-
-
+typedef struct {
+ long quot;
+ long rem;
+} ldiv_t;
/* Return the `ldiv_t' representation of NUMER over DENOM. */
ldiv_t
ldiv (long int numer, long int denom)
#endif /* not MSDOS, or __TURBOC__ */
#endif /* not sparc. */
#endif /* not GNU C. */
-#ifdef __CPLUSPLUS__ /* dont know what this should be */
+#ifdef __cplusplus
extern "C" {
#endif
void* alloca(size_t);
-#ifdef __CPLUSPLUS__ /* dont know what this should be */
+#ifdef __cplusplus
}
#endif
#endif /* alloca not defined. */
#include <sys/time.h>
#include "serial.h"
-#ifdef __sun__
+#if defined(__sun__) || defined(__OpenBSD__) || defined(__FreeBSD__) || defined(__NetBSD__)
static struct termios tios = { BRKINT, 0, B115200|CS8|CREAD, 0, { 0 } };
#else
static struct termios tios = { BRKINT, 0, B115200|CS8|CREAD, 0, 0 };
#ifdef B307200
{ "307200", B307200 },
#endif
+#ifdef B460800
{ "460800", B460800 }
+#endif
};
static int nspeeds = sizeof speedmap / sizeof speedmap[0];
#include <unistd.h>
#include <errno.h>
+#ifdef __BEOS__
+#include <inttypes.h>
+#endif
+
extern int errno;
/*************************************************************************
projects / users / rw / ppcboot.git / commitdiff