* leave all fields at HW default values.
         */
        if (IS_GEN(dev_priv, 11)) {
-               if (intel_dsi_bitrate(intel_dsi) <= 800000) {
+               if (afe_clk(encoder) <= 800000) {
                        for_each_dsi_port(port, intel_dsi->ports) {
                                tmp = I915_READ(DPHY_TA_TIMING_PARAM(port));
                                tmp &= ~TA_SURE_MASK;
                        tmp |= EOTP_DISABLED;
 
                /* enable link calibration if freq > 1.5Gbps */
-               if (intel_dsi_bitrate(intel_dsi) >= 1500 * 1000) {
+               if (afe_clk(encoder) >= 1500 * 1000) {
                        tmp &= ~LINK_CALIBRATION_MASK;
                        tmp |= CALIBRATION_ENABLED_INITIAL_ONLY;
                }
         * TIME_NS = (BYTE_CLK_COUNT * 8 * 10^6)/ Bitrate
         * ESCAPE_CLK_COUNT  = TIME_NS/ESC_CLK_NS
         */
-       divisor = intel_dsi_tlpx_ns(intel_dsi) * intel_dsi_bitrate(intel_dsi) * 1000;
+       divisor = intel_dsi_tlpx_ns(intel_dsi) * afe_clk(encoder) * 1000;
        mul = 8 * 1000000;
        hs_tx_timeout = DIV_ROUND_UP(intel_dsi->hs_tx_timeout * mul,
                                     divisor);
                pipe_config->pipe_bpp = 18;
 
        pipe_config->clock_set = true;
-       pipe_config->port_clock = intel_dsi_bitrate(intel_dsi) / 5;
+       pipe_config->port_clock = afe_clk(encoder) / 5;
 
        return 0;
 }