drm/i915: Sort bdw+ pipe interrupt bits

It's really hard to figure out which bdw+ pipe interrupt bits
we've defined and which we have not. Sort the defines to make
that a bit easier (still not super easy since the bits have
been shuffled a bit over the years).

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240605111832.21373-4-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index caeeecc516e21b4493911c959f848c53289623f3..01112d15b86c42f2c967296102c5e4ad9dd7e315 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2503,29 +2503,29 @@
 #define  GEN8_PIPE_CDCLK_CRC_ERROR     REG_BIT(29)
 #define  GEN8_PIPE_CDCLK_CRC_DONE      REG_BIT(28)
 #define  XELPD_PIPE_SOFT_UNDERRUN      REG_BIT(22) /* adl/dg2+ */
-#define  XELPD_PIPE_HARD_UNDERRUN      REG_BIT(21) /* adl/dg2+ */
-#define  GEN12_PIPE_VBLANK_UNMOD       REG_BIT(19) /* tgl+ */
-#define  GEN8_PIPE_CURSOR_FAULT                REG_BIT(10) /* bdw */
-#define  GEN8_PIPE_SPRITE_FAULT                REG_BIT(9) /* bdw */
-#define  GEN8_PIPE_PRIMARY_FAULT       REG_BIT(8) /* bdw */
-#define  GEN8_PIPE_SPRITE_FLIP_DONE    REG_BIT(5) /* bdw */
-#define  GEN8_PIPE_PRIMARY_FLIP_DONE   REG_BIT(4) /* bdw */
-#define  GEN8_PIPE_SCAN_LINE_EVENT     REG_BIT(2)
-#define  GEN8_PIPE_VSYNC               REG_BIT(1)
-#define  GEN8_PIPE_VBLANK              REG_BIT(0)
-#define  GEN9_PIPE_CURSOR_FAULT                REG_BIT(11) /* skl+ */
 #define  GEN11_PIPE_PLANE7_FAULT       REG_BIT(22) /* icl/tgl */
+#define  XELPD_PIPE_HARD_UNDERRUN      REG_BIT(21) /* adl/dg2+ */
 #define  GEN11_PIPE_PLANE6_FAULT       REG_BIT(21) /* icl/tgl */
 #define  GEN11_PIPE_PLANE5_FAULT       REG_BIT(20) /* icl+ */
+#define  GEN12_PIPE_VBLANK_UNMOD       REG_BIT(19) /* tgl+ */
+#define  GEN9_PIPE_CURSOR_FAULT                REG_BIT(11) /* skl+ */
 #define  GEN9_PIPE_PLANE4_FAULT                REG_BIT(10) /* skl+ */
+#define  GEN8_PIPE_CURSOR_FAULT                REG_BIT(10) /* bdw */
 #define  GEN9_PIPE_PLANE3_FAULT                REG_BIT(9) /* skl+ */
+#define  GEN8_PIPE_SPRITE_FAULT                REG_BIT(9) /* bdw */
 #define  GEN9_PIPE_PLANE2_FAULT                REG_BIT(8) /* skl+ */
+#define  GEN8_PIPE_PRIMARY_FAULT       REG_BIT(8) /* bdw */
 #define  GEN9_PIPE_PLANE1_FAULT                REG_BIT(7) /* skl+ */
 #define  GEN9_PIPE_PLANE4_FLIP_DONE    REG_BIT(6) /* skl+ */
 #define  GEN9_PIPE_PLANE3_FLIP_DONE    REG_BIT(5) /* skl+ */
+#define  GEN8_PIPE_SPRITE_FLIP_DONE    REG_BIT(5) /* bdw */
 #define  GEN9_PIPE_PLANE2_FLIP_DONE    REG_BIT(4) /* skl+ */
+#define  GEN8_PIPE_PRIMARY_FLIP_DONE   REG_BIT(4) /* bdw */
 #define  GEN9_PIPE_PLANE1_FLIP_DONE    REG_BIT(3) /* skl+ */
 #define  GEN9_PIPE_PLANE_FLIP_DONE(p)  REG_BIT(3 + (p)) /* skl+ */
+#define  GEN8_PIPE_SCAN_LINE_EVENT     REG_BIT(2)
+#define  GEN8_PIPE_VSYNC               REG_BIT(1)
+#define  GEN8_PIPE_VBLANK              REG_BIT(0)
 #define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \
        (GEN8_PIPE_CURSOR_FAULT | \
         GEN8_PIPE_SPRITE_FAULT | \