riscv, bpf: use lw when reading int cpu in BPF_MOV64_PERCPU_REG

emit_ld is wrong, because thread_info.cpu is 32-bit, not xlen-bit wide.
The struct currently has a hole after cpu, so little endian accesses
seemed fine.

Fixes: 19c56d4e5be1 ("riscv, bpf: add internal-only MOV instruction to resolve per-CPU addrs")
Cc: stable@vger.kernel.org
Signed-off-by: Radim Krčmář <rkrcmar@ventanamicro.com>
Reviewed-by: Pu Lehui <pulehui@huawei.com>
Acked-by: Björn Töpel <bjorn@kernel.org>
Tested-by: Björn Töpel <bjorn@rivosinc.com> # QEMU
Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Link: https://lore.kernel.org/r/20250812090256.757273-3-rkrcmar@ventanamicro.com
Signed-off-by: Paul Walmsley <pjw@kernel.org>

diff --git a/arch/riscv/net/bpf_jit_comp64.c b/arch/riscv/net/bpf_jit_comp64.c
index 10e01ff06312d9f1e6e213bb069c6ea749ea9af2..6e1554d89681ff97ffd036974838a8c2dfef9320 100644 (file)
--- a/arch/riscv/net/bpf_jit_comp64.c
+++ b/arch/riscv/net/bpf_jit_comp64.c
@@ -1356,7 +1356,7 @@ int bpf_jit_emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx,
                                emit_mv(rd, rs, ctx);
 #ifdef CONFIG_SMP
                        /* Load current CPU number in T1 */
-                       emit_ld(RV_REG_T1, offsetof(struct thread_info, cpu),
+                       emit_lw(RV_REG_T1, offsetof(struct thread_info, cpu),
                                RV_REG_TP, ctx);
                        /* Load address of __per_cpu_offset array in T2 */
                        emit_addr(RV_REG_T2, (u64)&__per_cpu_offset, extra_pass, ctx);