{
        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
        struct hw_perf_event *hwc = &event->hw;
-       u64 val = cpuc->pebs_enabled;
 
        hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT;
 
-       val |= 1ULL << hwc->idx;
+       cpuc->pebs_enabled |= 1ULL << hwc->idx;
        WARN_ON_ONCE(cpuc->enabled);
 
        if (x86_pmu.intel_cap.pebs_trap)
 {
        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
        struct hw_perf_event *hwc = &event->hw;
-       u64 val = cpuc->pebs_enabled;
 
-       val &= ~(1ULL << hwc->idx);
+       cpuc->pebs_enabled &= ~(1ULL << hwc->idx);
        if (cpuc->enabled)
-               wrmsrl(MSR_IA32_PEBS_ENABLE, val);
+               wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
 
        hwc->config |= ARCH_PERFMON_EVENTSEL_INT;