drm/i915: pass dev_priv explicitly to PORT_ALPM_LFPS_CTL

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PORT_ALPM_LFPS_CTL register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/f8a3bbade94258852b8129c5f5918fb06ceab54b.1714471597.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index b93953a00deb377e94f4198b4161c2b36bb58eb9..595eb1b3b6c6afdf21dd54ae7c5ec8afeff11dc1 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1798,7 +1798,8 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp)
                               PORT_ALPM_CTL_SILENCE_PERIOD(
                                       psr->alpm_parameters.silence_period_sym_clocks));
 
-               intel_de_write(dev_priv, PORT_ALPM_LFPS_CTL(cpu_transcoder),
+               intel_de_write(dev_priv,
+                              PORT_ALPM_LFPS_CTL(dev_priv, cpu_transcoder),
                               PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(10) |
                               PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION(
                                       psr->alpm_parameters.lfps_half_cycle_num_of_syms) |

diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
index eea6abe0ecfa185a8ba80ca906d60909224375b1..e14cb48f2614102a619ef40810b268b309da79d5 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
@@ -345,7 +345,7 @@
 #define  PORT_ALPM_CTL_SILENCE_PERIOD(val)     REG_FIELD_PREP(PORT_ALPM_CTL_SILENCE_PERIOD_MASK, val)
 
 #define _PORT_ALPM_LFPS_CTL_A                                  0x16fa30
-#define PORT_ALPM_LFPS_CTL(tran)                               _MMIO_TRANS2(dev_priv, tran, _PORT_ALPM_LFPS_CTL_A)
+#define PORT_ALPM_LFPS_CTL(dev_priv, tran)                             _MMIO_TRANS2(dev_priv, tran, _PORT_ALPM_LFPS_CTL_A)
 #define  PORT_ALPM_LFPS_CTL_LFPS_START_POLARITY                        REG_BIT(31)
 #define  PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MASK              REG_GENMASK(27, 24)
 #define  PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MIN               7