riscv: dts: microchip: add a device tree for Discovery Kit

Add a minimal device tree for the Microchip PolarFire SoC Discovery Kit.
The Discovery Kit is a cost-optimized board based on PolarFire SoC
MPFS095T and features:

- 1 GB DDR4x16
- 1x Gigabit Ethernet
- 3x UARTs
- Raspberry Pi connector
- mikroBus connector
- microSD card connector

Link: https://www.microchip.com/en-us/development-tool/mpfs-disco-kit
Signed-off-by: Valentina Fernandez <valentina.fernandezalanis@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile
index 1e2f4e41bf0d85c6957c84dcac0b5f588892ebe5..345ed7a48cc103caca7bbd7340a0e0970aa64a08 100644 (file)
--- a/arch/riscv/boot/dts/microchip/Makefile
+++ b/arch/riscv/boot/dts/microchip/Makefile
@@ -1,5 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0
 dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-beaglev-fire.dtb
+dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-disco-kit.dtb
 dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-icicle-kit.dtb
 dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-icicle-kit-prod.dtb
 dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-m100pfsevp.dtb

diff --git a/arch/riscv/boot/dts/microchip/mpfs-disco-kit-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-disco-kit-fabric.dtsi
new file mode 100644 (file)
index 0000000..ae8be7d
--- /dev/null
+++ b/arch/riscv/boot/dts/microchip/mpfs-disco-kit-fabric.dtsi
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2020-2025 Microchip Technology Inc */
+
+/ {
+       core_pwm0: pwm@40000000 {
+               compatible = "microchip,corepwm-rtl-v4";
+               reg = <0x0 0x40000000 0x0 0xF0>;
+               microchip,sync-update-mask = /bits/ 32 <0>;
+               #pwm-cells = <3>;
+               clocks = <&ccc_sw CLK_CCC_PLL0_OUT3>;
+               status = "disabled";
+       };
+
+       i2c2: i2c@40000200 {
+               compatible = "microchip,corei2c-rtl-v7";
+               reg = <0x0 0x40000200 0x0 0x100>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               clocks = <&ccc_sw CLK_CCC_PLL0_OUT3>;
+               interrupt-parent = <&plic>;
+               interrupts = <122>;
+               clock-frequency = <100000>;
+               status = "disabled";
+       };
+
+       ihc: mailbox {
+               compatible = "microchip,sbi-ipc";
+               interrupt-parent = <&plic>;
+               interrupts = <180>, <179>, <178>, <177>;
+               interrupt-names = "hart-1", "hart-2", "hart-3", "hart-4";
+               #mbox-cells = <1>;
+               status = "disabled";
+       };
+
+       mailbox@50000000 {
+               compatible = "microchip,miv-ihc-rtl-v2";
+               reg = <0x0 0x50000000 0x0 0x1c000>;
+               interrupt-parent = <&plic>;
+               interrupts = <180>, <179>, <178>, <177>;
+               interrupt-names = "hart-1", "hart-2", "hart-3", "hart-4";
+               #mbox-cells = <1>;
+               microchip,ihc-chan-disabled-mask = /bits/ 16 <0>;
+               status = "disabled";
+       };
+
+       refclk_ccc: clock-cccref {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+       };
+};
+
+&ccc_sw {
+       clocks = <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>,
+                <&refclk_ccc>, <&refclk_ccc>;
+       clock-names = "pll0_ref0", "pll0_ref1", "pll1_ref0", "pll1_ref1",
+                     "dll0_ref", "dll1_ref";
+       status = "okay";
+};

diff --git a/arch/riscv/boot/dts/microchip/mpfs-disco-kit.dts b/arch/riscv/boot/dts/microchip/mpfs-disco-kit.dts
new file mode 100644 (file)
index 0000000..c068b9b
--- /dev/null
+++ b/arch/riscv/boot/dts/microchip/mpfs-disco-kit.dts
@@ -0,0 +1,190 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2020-2025 Microchip Technology Inc */
+
+/dts-v1/;
+
+#include "mpfs.dtsi"
+#include "mpfs-disco-kit-fabric.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+       model = "Microchip PolarFire-SoC Discovery Kit";
+       compatible = "microchip,mpfs-disco-kit-reference-rtl-v2507",
+                    "microchip,mpfs-disco-kit",
+                    "microchip,mpfs";
+
+       aliases {
+               ethernet0 = &mac0;
+               serial4 = &mmuart4;
+       };
+
+       chosen {
+               stdout-path = "serial4:115200n8";
+       };
+
+       leds {
+               compatible = "gpio-leds";
+
+               led-1 {
+                       gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>;
+                       color = <LED_COLOR_ID_AMBER>;
+                       label = "led1";
+               };
+
+               led-2 {
+                       gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>;
+                       color = <LED_COLOR_ID_RED>;
+                       label = "led2";
+               };
+
+               led-3 {
+                       gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+                       color = <LED_COLOR_ID_AMBER>;
+                       label = "led3";
+               };
+
+               led-4 {
+                       gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
+                       color = <LED_COLOR_ID_RED>;
+                       label = "led4";
+               };
+
+               led-5 {
+                       gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
+                       color = <LED_COLOR_ID_AMBER>;
+                       label = "led5";
+               };
+
+               led-6 {
+                       gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>;
+                       color = <LED_COLOR_ID_RED>;
+                       label = "led6";
+               };
+
+               led-7 {
+                       gpios = <&gpio2 23 GPIO_ACTIVE_HIGH>;
+                       color = <LED_COLOR_ID_AMBER>;
+                       label = "led7";
+               };
+
+               led-8 {
+                       gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+                       color = <LED_COLOR_ID_RED>;
+                       label = "led8";
+               };
+       };
+
+       ddrc_cache_lo: memory@80000000 {
+               device_type = "memory";
+               reg = <0x0 0x80000000 0x0 0x40000000>;
+       };
+
+       reserved-memory {
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               hss_payload: region@bfc00000 {
+                       reg = <0x0 0xbfc00000 0x0 0x400000>;
+                       no-map;
+               };
+       };
+};
+
+&core_pwm0 {
+       status = "okay";
+};
+
+&gpio1 {
+       interrupts = <27>, <28>, <29>, <30>,
+                    <31>, <32>, <33>, <47>,
+                    <35>, <36>, <37>, <38>,
+                    <39>, <40>, <41>, <42>,
+                    <43>, <44>, <45>, <46>,
+                    <47>, <48>, <49>, <50>;
+       status = "okay";
+};
+
+&gpio2 {
+       interrupts = <53>, <53>, <53>, <53>,
+                    <53>, <53>, <53>, <53>,
+                    <53>, <53>, <53>, <53>,
+                    <53>, <53>, <53>, <53>,
+                    <53>, <53>, <53>, <53>,
+                    <53>, <53>, <53>, <53>,
+                    <53>, <53>, <53>, <53>,
+                    <53>, <53>, <53>, <53>;
+       status = "okay";
+};
+
+&i2c0 {
+       status = "okay";
+};
+
+&i2c2 {
+       status = "okay";
+};
+
+&ihc {
+       status = "okay";
+};
+
+&mac0 {
+       phy-mode = "sgmii";
+       phy-handle = <&phy0>;
+       status = "okay";
+
+       phy0: ethernet-phy@b {
+               reg = <0xb>;
+       };
+};
+
+&mbox {
+       status = "okay";
+};
+
+&mmc {
+       bus-width = <4>;
+       disable-wp;
+       cap-sd-highspeed;
+       cap-mmc-highspeed;
+       sd-uhs-sdr12;
+       sd-uhs-sdr25;
+       sd-uhs-sdr50;
+       sd-uhs-sdr104;
+       no-1-8-v;
+       status = "okay";
+};
+
+&mmuart1 {
+       status = "okay";
+};
+
+&mmuart4 {
+       status = "okay";
+};
+
+&refclk {
+       clock-frequency = <125000000>;
+};
+
+&refclk_ccc {
+       clock-frequency = <50000000>;
+};
+
+&rtc {
+       status = "okay";
+};
+
+&spi0 {
+       status = "okay";
+};
+
+&spi1 {
+       status = "okay";
+};
+
+&syscontroller {
+       status = "okay";
+};