drm/i915/psr: Panel replay has to be enabled before link training

Panel replay has to be enabled on sink side before link training. Take this
into account in fastset check and in initial fastset check.

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240405113602.992714-9-jouni.hogander@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index a481c92181386644331e984cbd3ff3bbb1279988..dc23312bc8081962fb24b4aedc8d6d0972e772df 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5298,6 +5298,18 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
                PIPE_CONF_CHECK_CSC(output_csc);
        }
 
+       /*
+        * Panel replay has to be enabled before link training. PSR doesn't have
+        * this requirement -> check these only if using panel replay
+        */
+       if (current_config->has_panel_replay || pipe_config->has_panel_replay) {
+               PIPE_CONF_CHECK_BOOL(has_psr);
+               PIPE_CONF_CHECK_BOOL(has_psr2);
+               PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch);
+               PIPE_CONF_CHECK_BOOL(enable_psr2_su_region_et);
+               PIPE_CONF_CHECK_BOOL(has_panel_replay);
+       }
+
        PIPE_CONF_CHECK_BOOL(double_wide);
 
        if (dev_priv->display.dpll.mgr)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 8b67cd62f1880bac0b055d92c6619f7ceb45075e..20f2d4d9d7b94ea0c664b6bccf1310e7ad8b846b 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3386,6 +3386,14 @@ bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
                fastset = false;
        }
 
+       if (CAN_PANEL_REPLAY(intel_dp)) {
+               drm_dbg_kms(&i915->drm,
+                           "[ENCODER:%d:%s] Forcing full modeset to compute panel replay state\n",
+                           encoder->base.base.id, encoder->base.name);
+               crtc_state->uapi.mode_changed = true;
+               fastset = false;
+       }
+
        return fastset;
 }
 

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 4355fb02d8fd099446e72d4b82fc2b8dcee9ca7e..4db6c19731e96eb3df73eef7e60e55c2f8bf0e3f 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -192,9 +192,6 @@
 #define CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support && \
                           (intel_dp)->psr.source_support)
 
-#define CAN_PANEL_REPLAY(intel_dp) ((intel_dp)->psr.sink_panel_replay_support && \
-                                   (intel_dp)->psr.source_panel_replay_support)
-
 bool intel_encoder_can_psr(struct intel_encoder *encoder)
 {
        if (intel_encoder_is_dp(encoder) || encoder->type == INTEL_OUTPUT_DP_MST)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
index 2537dcb8765ce49b0b4211af2ebbac20a0240dcf..d483c85870e1db2e77da54aacc385518aba2eb78 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -21,6 +21,9 @@ struct intel_encoder;
 struct intel_plane;
 struct intel_plane_state;
 
+#define CAN_PANEL_REPLAY(intel_dp) ((intel_dp)->psr.sink_panel_replay_support && \
+                                   (intel_dp)->psr.source_panel_replay_support)
+
 bool intel_encoder_can_psr(struct intel_encoder *encoder);
 void intel_psr_init_dpcd(struct intel_dp *intel_dp);
 void intel_psr_enable_sink(struct intel_dp *intel_dp,