selftests/powerpc/pmu/: Add interface test for mmcr2_l2l3 field

The testcases uses event code 0x010000046080 to verify the l2l3 bit
setting for Monitor Mode Control Register 2 (MMCR2). check if this bit
is set correctly via perf interface in ISA v3.1 platform.

Signed-off-by: Madhavan Srinivasan <maddy@linux.ibm.com>
[mpe: Add error checking, drop GET_MMCR_FIELD, add to .gitignore]
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20220127072012.662451-18-kjain@linux.ibm.com

diff --git a/tools/testing/selftests/powerpc/pmu/sampling_tests/.gitignore b/tools/testing/selftests/powerpc/pmu/sampling_tests/.gitignore
index f0ad66d78ee0b3d4264a8021eee47d906c796699..84bfc4d0e51c9c66d619e20dfbaf5a1a9906ec49 100644 (file)
--- a/tools/testing/selftests/powerpc/pmu/sampling_tests/.gitignore
+++ b/tools/testing/selftests/powerpc/pmu/sampling_tests/.gitignore
@@ -5,3 +5,4 @@ mmcr0_pmcjce_test
 mmcr0_fc56_pmc1ce_test
 mmcr0_fc56_pmc56_test
 mmcr1_comb_test
+mmcr2_l2l3_test

diff --git a/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile b/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
index da87ffddc56847587350e5819e9b144e169f5421..ec4c758e91a9c5d7811da4710a4a5779598c3bb0 100644 (file)
--- a/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
+++ b/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
@@ -3,7 +3,7 @@ CFLAGS += -m64
 
 TEST_GEN_PROGS := mmcr0_exceptionbits_test mmcr0_cc56run_test mmcr0_pmccext_test \
                   mmcr0_pmcjce_test mmcr0_fc56_pmc1ce_test mmcr0_fc56_pmc56_test \
-                  mmcr1_comb_test
+                  mmcr1_comb_test mmcr2_l2l3_test
 
 top_srcdir = ../../../../../..
 include ../../../lib.mk

diff --git a/tools/testing/selftests/powerpc/pmu/sampling_tests/mmcr2_l2l3_test.c b/tools/testing/selftests/powerpc/pmu/sampling_tests/mmcr2_l2l3_test.c
new file mode 100644 (file)
index 0000000..ceca597
--- /dev/null
+++ b/tools/testing/selftests/powerpc/pmu/sampling_tests/mmcr2_l2l3_test.c
@@ -0,0 +1,74 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright 2022, Madhavan Srinivasan, IBM Corp.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+
+#include "../event.h"
+#include "misc.h"
+#include "utils.h"
+
+/* All successful D-side store dispatches for this thread */
+#define EventCode 0x010000046080
+
+#define MALLOC_SIZE     (0x10000 * 10)  /* Ought to be enough .. */
+
+/*
+ * A perf sampling test for mmcr2
+ * fields : l2l3
+ */
+static int mmcr2_l2l3(void)
+{
+       struct event event;
+       u64 *intr_regs;
+       char *p;
+       int i;
+
+       /* Check for platform support for the test */
+       SKIP_IF(check_pvr_for_sampling_tests());
+       SKIP_IF(!have_hwcap2(PPC_FEATURE2_ARCH_3_1));
+
+       /* Init the event for the sampling test */
+       event_init_sampling(&event, EventCode);
+       event.attr.sample_regs_intr = platform_extended_mask;
+       FAIL_IF(event_open(&event));
+       event.mmap_buffer = event_sample_buf_mmap(event.fd, 1);
+
+       FAIL_IF(event_enable(&event));
+
+       /* workload to make the event overflow */
+       p = malloc(MALLOC_SIZE);
+       FAIL_IF(!p);
+
+       for (i = 0; i < MALLOC_SIZE; i += 0x10000)
+               p[i] = i;
+
+       FAIL_IF(event_disable(&event));
+
+       /* Check for sample count */
+       FAIL_IF(!collect_samples(event.mmap_buffer));
+
+       intr_regs = get_intr_regs(&event, event.mmap_buffer);
+
+       /* Check for intr_regs */
+       FAIL_IF(!intr_regs);
+
+       /*
+        * Verify that l2l3 field of MMCR2 match with
+        * corresponding event code field
+        */
+       FAIL_IF(EV_CODE_EXTRACT(event.attr.config, l2l3) !=
+               get_mmcr2_l2l3(get_reg_value(intr_regs, "MMCR2"), 4));
+
+       event_close(&event);
+       free(p);
+
+       return 0;
+}
+
+int main(void)
+{
+       return test_harness(mmcr2_l2l3, "mmcr2_l2l3");
+}