} while (++i < 6);
 }
 
+static void __set_engine_usage_record(struct intel_engine_cs *engine,
+                                     u32 last_in, u32 id, u32 total)
+{
+       struct iosys_map rec_map = intel_guc_engine_usage_record_map(engine);
+
+#define record_write(map_, field_, val_) \
+       iosys_map_wr_field(map_, 0, struct guc_engine_usage_record, field_, val_)
+
+       record_write(&rec_map, last_switch_in_stamp, last_in);
+       record_write(&rec_map, current_context_index, id);
+       record_write(&rec_map, total_runtime, total);
+
+#undef record_write
+}
+
 static void guc_update_engine_gt_clks(struct intel_engine_cs *engine)
 {
        struct intel_engine_guc_stats *stats = &engine->stats.guc;
 
 static int guc_action_enable_usage_stats(struct intel_guc *guc)
 {
+       struct intel_gt *gt = guc_to_gt(guc);
+       struct intel_engine_cs *engine;
+       enum intel_engine_id id;
        u32 offset = intel_guc_engine_usage_offset(guc);
        u32 action[] = {
                INTEL_GUC_ACTION_SET_ENG_UTIL_BUFF,
                0,
        };
 
+       for_each_engine(engine, gt, id)
+               __set_engine_usage_record(engine, 0, 0xffffffff, 0);
+
        return intel_guc_send(guc, action, ARRAY_SIZE(action));
 }