arm64: dts: renesas: gray-hawk-single: Add CAN-FD support

Enable confirmed-working CAN-FD channels 0 and 1 on the Gray Hawk Single
development board:
  - Channel 0 uses an NXP TJR1443AT CAN transceiver, which must be
    enabled through a GPIO,
  - Channels 1-3 use Microchip MCP2558FD-H/SN CAN transceivers, which do
    not need explicit description, but channels 2-3 do not seem to work.

Inspired by a patch for Gray Hawk in the BSP by Duy Nguyen.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/7c2a06b7abec4ce1025761003ccdbce559789708.1722519717.git.geert+renesas@glider.be

diff --git a/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts b/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts
index 88f813562832c21b2e9e56620950cc02dfc9735f..9a1917b87f6138af053e2530e9c55177ecdd0126 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts
+++ b/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts
@@ -47,6 +47,13 @@
                ethernet0 = &avb0;
        };
 
+       can_transceiver0: can-phy0 {
+               compatible = "nxp,tjr1443";
+               #phy-cells = <0>;
+               enable-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
+               max-bitrate = <5000000>;
+       };
+
        chosen {
                bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
                stdout-path = "serial0:921600n8";
@@ -174,6 +181,25 @@
        };
 };
 
+&can_clk {
+       clock-frequency = <40000000>;
+};
+
+&canfd {
+       pinctrl-0 = <&canfd0_pins>, <&canfd1_pins>, <&can_clk_pins>;
+       pinctrl-names = "default";
+       status = "okay";
+
+       channel0 {
+               status = "okay";
+               phys = <&can_transceiver0>;
+       };
+
+       channel1 {
+               status = "okay";
+       };
+};
+
 &extal_clk {
        clock-frequency = <16666666>;
 };
@@ -305,6 +331,21 @@
                };
        };
 
+       can_clk_pins: can-clk {
+               groups = "can_clk";
+               function = "can_clk";
+       };
+
+       canfd0_pins: canfd0 {
+               groups = "canfd0_data";
+               function = "canfd0";
+       };
+
+       canfd1_pins: canfd1 {
+               groups = "canfd1_data";
+               function = "canfd1";
+       };
+
        hscif0_pins: hscif0 {
                groups = "hscif0_data", "hscif0_ctrl";
                function = "hscif0";