]> www.infradead.org Git - users/hch/misc.git/commitdiff
drm/amd/pm: Add debug bit for smu pool allocation
authorLijo Lazar <lijo.lazar@amd.com>
Fri, 7 Mar 2025 05:41:23 +0000 (11:11 +0530)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 19 Mar 2025 19:56:13 +0000 (15:56 -0400)
In certain cases, it's desirable to avoid PMFW log transactions to
system memory. Add a mask bit to decide whether to allocate smu pool in
device memory or system memory.

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

index f62456da0ba5b9abe0082b3ea97f944ebaf0915e..e3767555e44104bb6b7b060336bec75904a39060 100644 (file)
@@ -139,6 +139,7 @@ enum AMDGPU_DEBUG_MASK {
        AMDGPU_DEBUG_ENABLE_RAS_ACA = BIT(4),
        AMDGPU_DEBUG_ENABLE_EXP_RESETS = BIT(5),
        AMDGPU_DEBUG_DISABLE_GPU_RING_RESET = BIT(6),
+       AMDGPU_DEBUG_SMU_POOL = BIT(7),
 };
 
 unsigned int amdgpu_vram_limit = UINT_MAX;
@@ -2238,6 +2239,10 @@ static void amdgpu_init_debug_options(struct amdgpu_device *adev)
                pr_info("debug: ring reset disabled\n");
                adev->debug_disable_gpu_ring_reset = true;
        }
+       if (amdgpu_debug_mask & AMDGPU_DEBUG_SMU_POOL) {
+               pr_info("debug: use vram for smu pool\n");
+               adev->pm.smu_debug_mask |= SMU_DEBUG_POOL_USE_VRAM;
+       }
 }
 
 static unsigned long amdgpu_fix_asic_type(struct pci_dev *pdev, unsigned long flags)
index 9fb26b5c8ae7aa1ada38c04a8edb2a82bdff33b0..f93d287dbf1376bf1257ea57bcdf7a25d4f26b29 100644 (file)
@@ -295,7 +295,8 @@ enum ip_power_state {
 };
 
 /* Used to mask smu debug modes */
-#define SMU_DEBUG_HALT_ON_ERROR                0x1
+#define SMU_DEBUG_HALT_ON_ERROR                BIT(0)
+#define SMU_DEBUG_POOL_USE_VRAM                BIT(1)
 
 #define MAX_SMU_I2C_BUSES       2
 
index d1aa6075c4f411b648366f1687f4126ca56c0185..033c3229b555f04e94bc1a1e4d2e170c8b88256b 100644 (file)
@@ -1027,7 +1027,10 @@ static int smu_alloc_memory_pool(struct smu_context *smu)
 
        memory_pool->size = pool_size;
        memory_pool->align = PAGE_SIZE;
-       memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT;
+       memory_pool->domain =
+               (adev->pm.smu_debug_mask & SMU_DEBUG_POOL_USE_VRAM) ?
+                       AMDGPU_GEM_DOMAIN_VRAM :
+                       AMDGPU_GEM_DOMAIN_GTT;
 
        switch (pool_size) {
        case SMU_MEMORY_POOL_SIZE_256_MB: