[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
                [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
                [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
+               [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
        },
 };
 
        },
 };
 
+static const struct dpu_wb_cfg sm6125_wb[] = {
+       {
+               .name = "wb_2", .id = WB_2,
+               .base = 0x65000, .len = 0x2c8,
+               .features = WB_SDM845_MASK,
+               .format_list = wb2_formats_rgb,
+               .num_formats = ARRAY_SIZE(wb2_formats_rgb),
+               .clk_ctrl = DPU_CLK_CTRL_WB2,
+               .xin_id = 6,
+               .vbif_idx = VBIF_RT,
+               .maxlinewidth = 2160,
+               .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
+       },
+};
+
 static const struct dpu_intf_cfg sm6125_intf[] = {
        {
                .name = "intf_0", .id = INTF_0,
        .dspp = sm6125_dspp,
        .pingpong_count = ARRAY_SIZE(sm6125_pp),
        .pingpong = sm6125_pp,
+       .wb_count = ARRAY_SIZE(sm6125_wb),
+       .wb = sm6125_wb,
        .intf_count = ARRAY_SIZE(sm6125_intf),
        .intf = sm6125_intf,
        .vbif_count = ARRAY_SIZE(sdm845_vbif),