(amdgpu_ip_block_mask & (1 << AMD_IP_BLOCK_TYPE_PSP)))
                psp_enabled = true;
 
-       if (amdgpu_sriov_vf(adev)) {
-               amdgpu_virt_init_setting(adev);
-               xgpu_ai_mailbox_set_irq_funcs(adev);
-       }
-
        /*
         * nbio need be used for both sdma and gfx9, but only
         * initializes once
                return -EINVAL;
        }
 
+       if (amdgpu_sriov_vf(adev)) {
+               amdgpu_virt_init_setting(adev);
+               xgpu_ai_mailbox_set_irq_funcs(adev);
+       }
+
        adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type);
 
        amdgpu_get_pcie_info(adev);
 
                (amdgpu_ip_block_mask & (1 << AMD_IP_BLOCK_TYPE_SMC)))
                smc_enabled = true;
 
-       if (amdgpu_sriov_vf(adev)) {
-               amdgpu_virt_init_setting(adev);
-               xgpu_vi_mailbox_set_irq_funcs(adev);
-       }
-
        adev->rev_id = vi_get_rev_id(adev);
        adev->external_rev_id = 0xFF;
        switch (adev->asic_type) {
                return -EINVAL;
        }
 
+       if (amdgpu_sriov_vf(adev)) {
+               amdgpu_virt_init_setting(adev);
+               xgpu_vi_mailbox_set_irq_funcs(adev);
+       }
+
        /* vi use smc load by default */
        adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type);