.ssp_base_offset = APL_SSP_BASE_OFFSET,
        .quirks = SOF_INTEL_PROCEN_FMT_QUIRK,
        .check_ipc_irq  = hda_dsp_check_ipc_irq,
+       .cl_init = cl_dsp_init,
        .hw_ip_version = SOF_INTEL_CAVS_1_5_PLUS,
 };
 EXPORT_SYMBOL_NS(apl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
 
        .sdw_alh_base = SDW_ALH_BASE,
        .check_sdw_irq  = hda_common_check_sdw_irq,
        .check_ipc_irq  = hda_dsp_check_ipc_irq,
+       .cl_init = cl_dsp_init,
        .hw_ip_version = SOF_INTEL_CAVS_1_8,
 };
 EXPORT_SYMBOL_NS(cnl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
        .sdw_alh_base = SDW_ALH_BASE,
        .check_sdw_irq  = hda_common_check_sdw_irq,
        .check_ipc_irq  = hda_dsp_check_ipc_irq,
+       .cl_init = cl_dsp_init,
        .hw_ip_version = SOF_INTEL_CAVS_2_0,
 };
 EXPORT_SYMBOL_NS(jsl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
 
  * power on all host managed cores and only unstall/run the boot core to boot the
  * DSP then turn off all non boot cores (if any) is powered on.
  */
-static int cl_dsp_init(struct snd_sof_dev *sdev, int stream_tag, bool imr_boot)
+int cl_dsp_init(struct snd_sof_dev *sdev, int stream_tag, bool imr_boot)
 {
        struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
        const struct sof_intel_dsp_desc *chip = hda->desc;
 
 static int hda_dsp_boot_imr(struct snd_sof_dev *sdev)
 {
+       const struct sof_intel_dsp_desc *chip_info;
        int ret;
 
-       ret = cl_dsp_init(sdev, 0, true);
+       chip_info = get_chip_info(sdev->pdata);
+       if (chip_info->cl_init)
+               ret = chip_info->cl_init(sdev, 0, true);
+       else
+               ret = -EINVAL;
+
        if (!ret)
                hda_sdw_process_wakeen(sdev);
 
                        "Attempting iteration %d of Core En/ROM load...\n", i);
 
                hda->boot_iteration = i + 1;
-               ret = cl_dsp_init(sdev, hext_stream->hstream.stream_tag, false);
+               if (chip_info->cl_init)
+                       ret = chip_info->cl_init(sdev, hext_stream->hstream.stream_tag, false);
+               else
+                       ret = -EINVAL;
 
                /* don't retry anymore if successful */
                if (!ret)
 
                                              int direction);
 int hda_cl_cleanup(struct snd_sof_dev *sdev, struct snd_dma_buffer *dmab,
                   struct hdac_ext_stream *hext_stream);
+int cl_dsp_init(struct snd_sof_dev *sdev, int stream_tag, bool imr_boot);
 #define HDA_CL_STREAM_FORMAT 0x40
 
 /* pre and post fw run ops */
 
        .sdw_alh_base = SDW_ALH_BASE,
        .check_sdw_irq  = hda_common_check_sdw_irq,
        .check_ipc_irq  = hda_dsp_check_ipc_irq,
+       .cl_init = cl_dsp_init,
        .hw_ip_version = SOF_INTEL_CAVS_2_0,
 };
 EXPORT_SYMBOL_NS(icl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
 
        enum sof_intel_hw_ip_version hw_ip_version;
        bool (*check_sdw_irq)(struct snd_sof_dev *sdev);
        bool (*check_ipc_irq)(struct snd_sof_dev *sdev);
+       int (*cl_init)(struct snd_sof_dev *sdev, int stream_tag, bool imr_boot);
 };
 
 extern struct snd_sof_dsp_ops sof_tng_ops;
 
        .sdw_alh_base = SDW_ALH_BASE,
        .check_sdw_irq  = hda_common_check_sdw_irq,
        .check_ipc_irq  = hda_dsp_check_ipc_irq,
+       .cl_init = cl_dsp_init,
        .hw_ip_version = SOF_INTEL_CAVS_2_5,
 };
 EXPORT_SYMBOL_NS(tgl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
        .sdw_alh_base = SDW_ALH_BASE,
        .check_sdw_irq  = hda_common_check_sdw_irq,
        .check_ipc_irq  = hda_dsp_check_ipc_irq,
+       .cl_init = cl_dsp_init,
        .hw_ip_version = SOF_INTEL_CAVS_2_5,
 };
 EXPORT_SYMBOL_NS(tglh_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
        .sdw_alh_base = SDW_ALH_BASE,
        .check_sdw_irq  = hda_common_check_sdw_irq,
        .check_ipc_irq  = hda_dsp_check_ipc_irq,
+       .cl_init = cl_dsp_init,
        .hw_ip_version = SOF_INTEL_CAVS_2_5,
 };
 EXPORT_SYMBOL_NS(ehl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
        .sdw_alh_base = SDW_ALH_BASE,
        .check_sdw_irq  = hda_common_check_sdw_irq,
        .check_ipc_irq  = hda_dsp_check_ipc_irq,
+       .cl_init = cl_dsp_init,
        .hw_ip_version = SOF_INTEL_CAVS_2_5,
 };
 EXPORT_SYMBOL_NS(adls_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);