MIPS: bitops: Avoid redundant zero-comparison for non-LLSC

The IRQ-disabling non-LLSC fallbacks for bitops on UP systems already
return a zero or one, so there's no need to perform another comparison
against zero. Move these comparisons into the LLSC paths to avoid the
redundant work.

Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@vger.kernel.org
Cc: Huacai Chen <chenhc@lemote.com>
Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: linux-kernel@vger.kernel.org

diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h
index 0f8ff896e86b11c301eb4af2ac61291286698f74..7671db2a7b732761e2a3ff0a1ce3cdb49b874369 100644 (file)
--- a/arch/mips/include/asm/bitops.h
+++ b/arch/mips/include/asm/bitops.h
@@ -264,6 +264,8 @@ static inline int test_and_set_bit_lock(unsigned long nr,
                : "=&r" (temp), "+m" (*m), "=&r" (res)
                : "ir" (BIT(bit))
                : __LLSC_CLOBBER);
+
+               res = res != 0;
        } else {
                loongson_llsc_mb();
                do {
@@ -279,12 +281,12 @@ static inline int test_and_set_bit_lock(unsigned long nr,
                        : __LLSC_CLOBBER);
                } while (unlikely(!res));
 
-               res = temp & BIT(bit);
+               res = (temp & BIT(bit)) != 0;
        }
 
        smp_llsc_mb();
 
-       return res != 0;
+       return res;
 }
 
 /*
@@ -335,6 +337,8 @@ static inline int test_and_clear_bit(unsigned long nr,
                : "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m), "=&r" (res)
                : "ir" (BIT(bit))
                : __LLSC_CLOBBER);
+
+               res = res != 0;
        } else if ((MIPS_ISA_REV >= 2) && __builtin_constant_p(nr)) {
                loongson_llsc_mb();
                do {
@@ -363,12 +367,12 @@ static inline int test_and_clear_bit(unsigned long nr,
                        : __LLSC_CLOBBER);
                } while (unlikely(!res));
 
-               res = temp & BIT(bit);
+               res = (temp & BIT(bit)) != 0;
        }
 
        smp_llsc_mb();
 
-       return res != 0;
+       return res;
 }
 
 /*
@@ -403,6 +407,8 @@ static inline int test_and_change_bit(unsigned long nr,
                : "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m), "=&r" (res)
                : "ir" (BIT(bit))
                : __LLSC_CLOBBER);
+
+               res = res != 0;
        } else {
                loongson_llsc_mb();
                do {
@@ -418,12 +424,12 @@ static inline int test_and_change_bit(unsigned long nr,
                        : __LLSC_CLOBBER);
                } while (unlikely(!res));
 
-               res = temp & BIT(bit);
+               res = (temp & BIT(bit)) != 0;
        }
 
        smp_llsc_mb();
 
-       return res != 0;
+       return res;
 }
 
 #include <asm-generic/bitops/non-atomic.h>