drm/amdgpu: add poison mode query for UMC

Add ras poison mode query interface for UMC.

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
index e5a75fb788ddb5105e485dc2fbfb88fd7050042b..1f5fe2315236d86a486bc340697a4b89796ef79d 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
@@ -48,6 +48,7 @@ struct amdgpu_umc_ras_funcs {
                                      void *ras_error_status);
        void (*query_ras_error_address)(struct amdgpu_device *adev,
                                        void *ras_error_status);
+       bool (*query_ras_poison_mode)(struct amdgpu_device *adev);
 };
 
 struct amdgpu_umc_funcs {

diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c b/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c
index bb30336b1e8d8c6a21540e4e9bda5c04fc2750f6..f7ec3fe134e52fd6c685b90b9c971da24378a28d 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c
+++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c
@@ -288,9 +288,43 @@ static void umc_v6_7_query_ras_error_address(struct amdgpu_device *adev,
        }
 }
 
+static uint32_t umc_v6_7_query_ras_poison_mode_per_channel(
+                                               struct amdgpu_device *adev,
+                                               uint32_t umc_reg_offset)
+{
+       uint32_t ecc_ctrl_addr, ecc_ctrl;
+
+       ecc_ctrl_addr =
+               SOC15_REG_OFFSET(UMC, 0, regUMCCH0_0_EccCtrl);
+       ecc_ctrl = RREG32_PCIE((ecc_ctrl_addr +
+                                       umc_reg_offset) * 4);
+
+       return REG_GET_FIELD(ecc_ctrl, UMCCH0_0_EccCtrl, UCFatalEn);
+}
+
+static bool umc_v6_7_query_ras_poison_mode(struct amdgpu_device *adev)
+{
+       uint32_t umc_inst        = 0;
+       uint32_t ch_inst         = 0;
+       uint32_t umc_reg_offset  = 0;
+
+       LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) {
+               umc_reg_offset = get_umc_v6_7_reg_offset(adev,
+                                                       umc_inst,
+                                                       ch_inst);
+               /* Enabling fatal error in one channel will be considered
+                  as fatal error mode */
+               if (umc_v6_7_query_ras_poison_mode_per_channel(adev, umc_reg_offset))
+                       return false;
+       }
+
+       return true;
+}
+
 const struct amdgpu_umc_ras_funcs umc_v6_7_ras_funcs = {
        .ras_late_init = amdgpu_umc_ras_late_init,
        .ras_fini = amdgpu_umc_ras_fini,
        .query_ras_error_count = umc_v6_7_query_ras_error_count,
        .query_ras_error_address = umc_v6_7_query_ras_error_address,
+       .query_ras_poison_mode = umc_v6_7_query_ras_poison_mode,
 };