x86/tsx: Add a feature bit for TSX control MSR support

Support for the TSX control MSR is enumerated in MSR_IA32_ARCH_CAPABILITIES.
This is different from how other CPU features are enumerated i.e. via
CPUID. Currently, a call to tsx_ctrl_is_supported() is required for
enumerating the feature. In the absence of a feature bit for TSX control,
any code that relies on checking feature bits directly will not work.

In preparation for adding a feature bit check in MSR save/restore
during suspend/resume, set a new feature bit X86_FEATURE_TSX_CTRL when
MSR_IA32_TSX_CTRL is present. Also make tsx_ctrl_is_supported() use the
new feature bit to avoid any overhead of reading the MSR.

  [ bp: Remove tsx_ctrl_is_supported(), add room for two more feature
    bits in word 11 which are coming up in the next merge window. ]

Suggested-by: Andrew Cooper <andrew.cooper3@citrix.com>
Signed-off-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Reviewed-by: Dave Hansen <dave.hansen@linux.intel.com>
Cc: <stable@kernel.org>
Link: https://lore.kernel.org/r/de619764e1d98afbb7a5fa58424f1278ede37b45.1668539735.git.pawan.kumar.gupta@linux.intel.com

diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index b71f4f2ecdd571a44a808e443118278ea30cbe04..b2da7cb64b317f32869c509555b6f70a400dc3ec 100644 (file)
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -305,6 +305,9 @@
 #define X86_FEATURE_USE_IBPB_FW                (11*32+16) /* "" Use IBPB during runtime firmware calls */
 #define X86_FEATURE_RSB_VMEXIT_LITE    (11*32+17) /* "" Fill RSB on VM exit when EIBRS is enabled */
 
+
+#define X86_FEATURE_MSR_TSX_CTRL       (11*32+20) /* "" MSR IA32_TSX_CTRL (Intel) implemented */
+
 /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
 #define X86_FEATURE_AVX_VNNI           (12*32+ 4) /* AVX VNNI instructions */
 #define X86_FEATURE_AVX512_BF16                (12*32+ 5) /* AVX512 BFLOAT16 instructions */

diff --git a/arch/x86/kernel/cpu/tsx.c b/arch/x86/kernel/cpu/tsx.c
index ec7bbac3a9f29aa4f34b5d9ba0de4d9c58381cc0..8009c8346d8f832016ded51bdafd6528fa072bb0 100644 (file)
--- a/arch/x86/kernel/cpu/tsx.c
+++ b/arch/x86/kernel/cpu/tsx.c
@@ -58,24 +58,6 @@ static void tsx_enable(void)
        wrmsrl(MSR_IA32_TSX_CTRL, tsx);
 }
 
-static bool tsx_ctrl_is_supported(void)
-{
-       u64 ia32_cap = x86_read_arch_cap_msr();
-
-       /*
-        * TSX is controlled via MSR_IA32_TSX_CTRL.  However, support for this
-        * MSR is enumerated by ARCH_CAP_TSX_MSR bit in MSR_IA32_ARCH_CAPABILITIES.
-        *
-        * TSX control (aka MSR_IA32_TSX_CTRL) is only available after a
-        * microcode update on CPUs that have their MSR_IA32_ARCH_CAPABILITIES
-        * bit MDS_NO=1. CPUs with MDS_NO=0 are not planned to get
-        * MSR_IA32_TSX_CTRL support even after a microcode update. Thus,
-        * tsx= cmdline requests will do nothing on CPUs without
-        * MSR_IA32_TSX_CTRL support.
-        */
-       return !!(ia32_cap & ARCH_CAP_TSX_CTRL_MSR);
-}
-
 static enum tsx_ctrl_states x86_get_tsx_auto_mode(void)
 {
        if (boot_cpu_has_bug(X86_BUG_TAA))
@@ -135,7 +117,7 @@ static void tsx_clear_cpuid(void)
                rdmsrl(MSR_TSX_FORCE_ABORT, msr);
                msr |= MSR_TFA_TSX_CPUID_CLEAR;
                wrmsrl(MSR_TSX_FORCE_ABORT, msr);
-       } else if (tsx_ctrl_is_supported()) {
+       } else if (cpu_feature_enabled(X86_FEATURE_MSR_TSX_CTRL)) {
                rdmsrl(MSR_IA32_TSX_CTRL, msr);
                msr |= TSX_CTRL_CPUID_CLEAR;
                wrmsrl(MSR_IA32_TSX_CTRL, msr);
@@ -158,7 +140,8 @@ static void tsx_dev_mode_disable(void)
        u64 mcu_opt_ctrl;
 
        /* Check if RTM_ALLOW exists */
-       if (!boot_cpu_has_bug(X86_BUG_TAA) || !tsx_ctrl_is_supported() ||
+       if (!boot_cpu_has_bug(X86_BUG_TAA) ||
+           !cpu_feature_enabled(X86_FEATURE_MSR_TSX_CTRL) ||
            !cpu_feature_enabled(X86_FEATURE_SRBDS_CTRL))
                return;
 
@@ -191,7 +174,20 @@ void __init tsx_init(void)
                return;
        }
 
-       if (!tsx_ctrl_is_supported()) {
+       /*
+        * TSX is controlled via MSR_IA32_TSX_CTRL.  However, support for this
+        * MSR is enumerated by ARCH_CAP_TSX_MSR bit in MSR_IA32_ARCH_CAPABILITIES.
+        *
+        * TSX control (aka MSR_IA32_TSX_CTRL) is only available after a
+        * microcode update on CPUs that have their MSR_IA32_ARCH_CAPABILITIES
+        * bit MDS_NO=1. CPUs with MDS_NO=0 are not planned to get
+        * MSR_IA32_TSX_CTRL support even after a microcode update. Thus,
+        * tsx= cmdline requests will do nothing on CPUs without
+        * MSR_IA32_TSX_CTRL support.
+        */
+       if (x86_read_arch_cap_msr() & ARCH_CAP_TSX_CTRL_MSR) {
+               setup_force_cpu_cap(X86_FEATURE_MSR_TSX_CTRL);
+       } else {
                tsx_ctrl_state = TSX_CTRL_NOT_SUPPORTED;
                return;
        }