static void ggtt_update_access_counter(struct xe_ggtt *ggtt)
{
+ struct xe_gt *gt = XE_WA(ggtt->tile->primary_gt, 22019338487) ? ggtt->tile->primary_gt :
+ ggtt->tile->media_gt;
+ u32 max_gtt_writes = XE_WA(ggtt->tile->primary_gt, 22019338487) ? 1100 : 63;
/*
* Wa_22019338487: GMD_ID is a RO register, a dummy write forces gunit
* to wait for completion of prior GTT writes before letting this through.
*/
lockdep_assert_held(&ggtt->lock);
- if ((++ggtt->access_count % 63) == 0) {
- xe_mmio_write32(ggtt->tile->media_gt, GMD_ID, 0x0);
+ if ((++ggtt->access_count % max_gtt_writes) == 0) {
+ xe_mmio_write32(gt, GMD_ID, 0x0);
ggtt->access_count = 0;
}
}
ggtt->size = GUC_GGTT_TOP;
if (GRAPHICS_VERx100(xe) >= 1270)
- ggtt->pt_ops = ggtt->tile->media_gt && XE_WA(ggtt->tile->media_gt, 22019338487) ?
+ ggtt->pt_ops = (ggtt->tile->media_gt &&
+ XE_WA(ggtt->tile->media_gt, 22019338487)) ||
+ XE_WA(ggtt->tile->primary_gt, 22019338487) ?
&xelpg_pt_wa_ops : &xelpg_pt_ops;
else
ggtt->pt_ops = &xelp_pt_ops;
int ret = 0;
if ((!xe_uc_fw_is_available(>->uc.gsc.fw) ||
- xe_uc_fw_is_loaded(>->uc.gsc.fw)) &&
- XE_WA(gt, 22019338487))
+ xe_uc_fw_is_loaded(>->uc.gsc.fw)) && XE_WA(gt, 22019338487))
ret = xe_guc_pc_restore_stashed_freq(>->uc.guc.pc);
return ret;
#define GT_FREQUENCY_SCALER 3
#define LNL_MERT_FREQ_CAP 800
+#define BMG_MERT_FREQ_CAP 2133
/**
* DOC: GuC Power Conservation (PC)
{
struct xe_gt *gt = pc_to_gt(pc);
- if (XE_WA(gt, 22019338487))
- return min(LNL_MERT_FREQ_CAP, pc->rp0_freq);
- else
+ if (XE_WA(gt, 22019338487)) {
+ if (xe_gt_is_media_type(gt))
+ return min(LNL_MERT_FREQ_CAP, pc->rp0_freq);
+ else
+ return min(BMG_MERT_FREQ_CAP, pc->rp0_freq);
+ } else {
return pc->rp0_freq;
+ }
}
/**