arm64: dts: exynosautov920: add cpucl1/2 clock DT nodes

Add cmu_cpucl1/2(CPU Cluster 1 and CPU Cluster 2) clocks
for switch, cluster domains respectively.

Signed-off-by: Shin Son <shin.son@samsung.com>
Link: https://lore.kernel.org/r/20250428113517.426987-5-shin.son@samsung.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

diff --git a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
index 9350c53f935e32f5ba0a7bdd3659b99859726e7a..2cb8041c8a9f86cc3e2faf829581f9e305233af3 100644 (file)
--- a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
@@ -1090,6 +1090,32 @@
                                      "cluster",
                                      "dbg";
                };
+
+               cmu_cpucl1: clock-controller@1ed00000 {
+                       compatible = "samsung,exynosautov920-cmu-cpucl1";
+                       reg = <0x1ed00000 0x8000>;
+                       #clock-cells = <1>;
+
+                       clocks = <&xtcxo>,
+                                <&cmu_top DOUT_CLKCMU_CPUCL1_SWITCH>,
+                                <&cmu_top DOUT_CLKCMU_CPUCL1_CLUSTER>;
+                       clock-names = "oscclk",
+                                     "switch",
+                                     "cluster";
+               };
+
+               cmu_cpucl2: clock-controller@1ee00000 {
+                       compatible = "samsung,exynosautov920-cmu-cpucl2";
+                       reg = <0x1ee00000 0x8000>;
+                       #clock-cells = <1>;
+
+                       clocks = <&xtcxo>,
+                                <&cmu_top DOUT_CLKCMU_CPUCL2_SWITCH>,
+                                <&cmu_top DOUT_CLKCMU_CPUCL2_CLUSTER>;
+                       clock-names = "oscclk",
+                                     "switch",
+                                     "cluster";
+               };
        };
 
        timer {