dev_err(&client->dev,
                        "Error %d initializing CHIP_CLK_CTRL\n", ret);
 
+       /* Mute everything to avoid pop from the following power-up */
+       ret = regmap_write(sgtl5000->regmap, SGTL5000_CHIP_ANA_CTRL,
+                          SGTL5000_CHIP_ANA_CTRL_DEFAULT);
+       if (ret) {
+               dev_err(&client->dev,
+                       "Error %d muting outputs via CHIP_ANA_CTRL\n", ret);
+               goto disable_clk;
+       }
+
+       /*
+        * If VAG is powered-on (e.g. from previous boot), it would be disabled
+        * by the write to ANA_POWER in later steps of the probe code. This
+        * may create a loud pop even with all outputs muted. The proper way
+        * to circumvent this is disabling the bit first and waiting the proper
+        * cool-down time.
+        */
+       ret = regmap_read(sgtl5000->regmap, SGTL5000_CHIP_ANA_POWER, &value);
+       if (ret) {
+               dev_err(&client->dev, "Failed to read ANA_POWER: %d\n", ret);
+               goto disable_clk;
+       }
+       if (value & SGTL5000_VAG_POWERUP) {
+               ret = regmap_update_bits(sgtl5000->regmap,
+                                        SGTL5000_CHIP_ANA_POWER,
+                                        SGTL5000_VAG_POWERUP,
+                                        0);
+               if (ret) {
+                       dev_err(&client->dev, "Error %d disabling VAG\n", ret);
+                       goto disable_clk;
+               }
+
+               msleep(SGTL5000_VAG_POWERDOWN_DELAY);
+       }
+
        /* Follow section 2.2.1.1 of AN3663 */
        ana_pwr = SGTL5000_ANA_POWER_DEFAULT;
        if (sgtl5000->num_supplies <= VDDD) {