arm64: dts: qcom: sm7180: remove assigned-clock-rate property for mdp clk

Drop the assigned clock rate property and vote on the mdp clock as per
calculated value during the usecase.

This patch is dependent on the patch ("drm/msm/disp/dpu1: set mdp clk
to the maximum frequency in opp table during probe") [1].

[1] https://lore.kernel.org/r/1647269217-14064-2-git-send-email-quic_vpolimer@quicinc.com/

Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1647919631-14447-4-git-send-email-quic_vpolimer@quicinc.com

diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 5dcaac23a1381681cef77d6f760c459fcb9a6035..3eb85cddd0be9ea232b8a3fca88fb6247cb9b09d 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -2896,9 +2896,6 @@
                                 <&dispcc DISP_CC_MDSS_MDP_CLK>;
                        clock-names = "iface", "ahb", "core";
 
-                       assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
-                       assigned-clock-rates = <300000000>;
-
                        interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
                        interrupt-controller;
                        #interrupt-cells = <1>;
@@ -2928,12 +2925,10 @@
                                         <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
                                clock-names = "bus", "iface", "rot", "lut", "core",
                                              "vsync";
-                               assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
-                                                 <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
+                               assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
                                                  <&dispcc DISP_CC_MDSS_ROT_CLK>,
                                                  <&dispcc DISP_CC_MDSS_AHB_CLK>;
-                               assigned-clock-rates = <300000000>,
-                                                      <19200000>,
+                               assigned-clock-rates = <19200000>,
                                                       <19200000>,
                                                       <19200000>;
                                operating-points-v2 = <&mdp_opp_table>;