ath9k_hw: Fix a reset failure on AR9382 (2x2).

AR9382 needs to be configured for the correct chain mask before
running AGC/TxIQ caliberation. Otherwise reset would fail.

Signed-off-by: Senthil Balasubramanian <senthilkumar@atheros.com>
Signed-off-by: Vasanthakumar Thiagarajan <vasanth@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>

diff --git a/drivers/net/wireless/ath/ath9k/ar9003_calib.c b/drivers/net/wireless/ath/ath9k/ar9003_calib.c
index 9e6edffe0bd125544bce11b4d1dbcea470173add..32eed19ff6f9fc3c6edb463ccec41ae260339a85 100644 (file)
--- a/drivers/net/wireless/ath/ath9k/ar9003_calib.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_calib.c
@@ -718,12 +718,19 @@ static bool ar9003_hw_init_cal(struct ath_hw *ah,
                               struct ath9k_channel *chan)
 {
        struct ath_common *common = ath9k_hw_common(ah);
+       int val;
 
-       /*
-        * 0x7 = 0b111 , AR9003 needs to be configured for 3-chain mode before
-        * running AGC/TxIQ cals
-        */
-       ar9003_hw_set_chain_masks(ah, 0x7, 0x7);
+       val = REG_READ(ah, AR_ENT_OTP);
+       ath_print(common, ATH_DBG_CALIBRATE, "ath9k: AR_ENT_OTP 0x%x\n", val);
+
+       if (val & AR_ENT_OTP_CHAIN2_DISABLE)
+               ar9003_hw_set_chain_masks(ah, 0x3, 0x3);
+       else
+               /*
+                * 0x7 = 0b111 , AR9003 needs to be configured for 3-chain
+                * mode before running AGC/TxIQ cals
+                */
+               ar9003_hw_set_chain_masks(ah, 0x7, 0x7);
 
        /* Do Tx IQ Calibration */
        ar9003_hw_tx_iq_cal(ah);

diff --git a/drivers/net/wireless/ath/ath9k/reg.h b/drivers/net/wireless/ath/ath9k/reg.h
index 42976b0a01c115692566fe0f7f416c5aa9949b9f..ac6a13e2735241beb01e87223809891f3fd276ec 100644 (file)
--- a/drivers/net/wireless/ath/ath9k/reg.h
+++ b/drivers/net/wireless/ath/ath9k/reg.h
@@ -1065,6 +1065,8 @@ enum {
 #define AR_INTR_PRIO_ASYNC_MASK   0x40c8
 #define AR_INTR_PRIO_SYNC_MASK    0x40cc
 #define AR_INTR_PRIO_ASYNC_ENABLE 0x40d4
+#define AR_ENT_OTP               0x40d8
+#define AR_ENT_OTP_CHAIN2_DISABLE               0x00020000
 
 #define AR_RTC_9300_PLL_DIV          0x000003ff
 #define AR_RTC_9300_PLL_DIV_S        0