sq->head = (sq->head + 1) % sq->size;
}
-static uint8_t nvme_cq_full(NvmeCQueue *cq)
+static inline bool nvme_cq_full(NvmeCQueue *cq)
{
return (cq->tail + 1) % cq->size == cq->head;
}
-static uint8_t nvme_sq_empty(NvmeSQueue *sq)
+static inline bool nvme_cq_empty(NvmeCQueue *cq)
+{
+ return cq->head == cq->tail;
+}
+
+static inline bool nvme_sq_empty(NvmeSQueue *sq)
{
return sq->head == sq->tail;
}
nvme_update_cq_head(cq);
- if (cq->tail == cq->head) {
+ if (nvme_cq_empty(cq)) {
if (cq->irq_enabled) {
n->cq_pending--;
}
/* Completion queue doorbell write */
uint16_t new_head = val & 0xffff;
- int start_sqs;
+ bool start_sqs;
NvmeCQueue *cq;
qid = (addr - (0x1000 + (1 << 2))) >> 3;
trace_pci_nvme_mmio_doorbell_cq(cq->cqid, new_head);
- start_sqs = nvme_cq_full(cq) ? 1 : 0;
+ start_sqs = nvme_cq_full(cq);
cq->head = new_head;
if (!qid && n->dbbuf_enabled) {
pci_dma_write(pci, cq->db_addr, &cq->head, sizeof(cq->head));
qemu_bh_schedule(cq->bh);
}
- if (cq->tail == cq->head) {
+ if (nvme_cq_empty(cq)) {
if (cq->irq_enabled) {
n->cq_pending--;
}