ARM: dts: imx6ul: align pin config nodes with bindings

Bindings expect pin configuration nodes in pinctrl to match certain
naming:

  imx6ul-kontron-bl.dtb: pinctrl@20e0000: 'usbotg1' does not match any of the regexes: 'grp$', 'pinctrl-[0-9]+'

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-14x14-evk.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-14x14-evk.dtsi
index 9cfb99ac9e9daaf5fe7479aee9dc8888909e4bdc..b74ee8948a781762bd798316ceac0c33258610f0 100644 (file)
--- a/arch/arm/boot/dts/nxp/imx/imx6ul-14x14-evk.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6ul-14x14-evk.dtsi
@@ -608,7 +608,7 @@
                >;
        };
 
-       pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+       pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp {
                fsl,pins = <
                        MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170b9
                        MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100b9
@@ -620,7 +620,7 @@
                >;
        };
 
-       pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+       pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp {
                fsl,pins = <
                        MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170f9
                        MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100f9

diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-ccimx6ulsbcexpress.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-ccimx6ulsbcexpress.dts
index ad7f63ca521a9d5d83ae2473b583796c0915b4ed..0d3b1ab82eabad413032ef23aa14723fd32d1277 100644 (file)
--- a/arch/arm/boot/dts/nxp/imx/imx6ul-ccimx6ulsbcexpress.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx6ul-ccimx6ulsbcexpress.dts
@@ -112,7 +112,7 @@
                >;
        };
 
-       pinctrl_ecspi3_master: ecspi3grp1 {
+       pinctrl_ecspi3_master: ecspi3-1-grp {
                fsl,pins = <
                        MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK    0x10b0
                        MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI      0x10b0
@@ -121,7 +121,7 @@
                >;
        };
 
-       pinctrl_ecspi3_slave: ecspi3grp2 {
+       pinctrl_ecspi3_slave: ecspi3-2-grp {
                fsl,pins = <
                        MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK    0x10b0
                        MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI      0x10b0

diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-ccimx6ulsbcpro.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-ccimx6ulsbcpro.dts
index ed61ae8524fa2a1445c7df50b2cdb03799b1c141..8aea8c99e2af59edb1d80e594cf0a67e975c05f5 100644 (file)
--- a/arch/arm/boot/dts/nxp/imx/imx6ul-ccimx6ulsbcpro.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx6ul-ccimx6ulsbcpro.dts
@@ -248,7 +248,7 @@
                >;
        };
 
-       pinctrl_ecspi1_master: ecspi1grp1 {
+       pinctrl_ecspi1_master: ecspi1-1-grp {
                fsl,pins = <
                        MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK       0x10b0
                        MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI       0x10b0
@@ -309,7 +309,7 @@
                >;
        };
 
-       pinctrl_lcdif_dat0_17: lcdifdatgrp0-17 {
+       pinctrl_lcdif_dat0_17: lcdifdat0-17-grp {
                fsl,pins = <
                        MX6UL_PAD_LCD_DATA00__LCDIF_DATA00      0x79
                        MX6UL_PAD_LCD_DATA01__LCDIF_DATA01      0x79
@@ -332,14 +332,14 @@
                >;
        };
 
-       pinctrl_lcdif_clken: lcdifctrlgrp1 {
+       pinctrl_lcdif_clken: lcdifctrl-1-grp {
                fsl,pins = <
                        MX6UL_PAD_LCD_CLK__LCDIF_CLK            0x17050
                        MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE      0x79
                >;
        };
 
-       pinctrl_lcdif_hvsync: lcdifctrlgrp2 {
+       pinctrl_lcdif_hvsync: lcdifctrl-2-grp {
                fsl,pins = <
                        MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC        0x79
                        MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC        0x79
@@ -370,7 +370,7 @@
                >;
        };
 
-       pinctrl_sai2_sleep: sai2grp-sleep {
+       pinctrl_sai2_sleep: sai2-sleep-grp {
                fsl,pins = <
                        MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15       0x3000
                        MX6UL_PAD_JTAG_TCK__GPIO1_IO14          0x3000
@@ -381,7 +381,7 @@
                >;
        };
 
-       pinctrl_uart2_4wires: uart2grp-4wires {
+       pinctrl_uart2_4wires: uart2-4wires-grp {
                fsl,pins = <
                        MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX   0x1b0b1
                        MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX   0x1b0b1
@@ -390,7 +390,7 @@
                >;
        };
 
-       pinctrl_uart3_2wires: uart3grp-2wires {
+       pinctrl_uart3_2wires: uart3-2wires-grp {
                fsl,pins = <
                        MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX   0x1b0b1
                        MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX   0x1b0b1

diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-ccimx6ulsom.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-ccimx6ulsom.dtsi
index 4a03ea6d24dc6f0d532d10e60557e1c8b109e748..9cc3eebb6b05e536ed16849434495f5852b695f6 100644 (file)
--- a/arch/arm/boot/dts/nxp/imx/imx6ul-ccimx6ulsom.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6ul-ccimx6ulsom.dtsi
@@ -232,7 +232,7 @@
                >;
        };
 
-       pinctrl_usdhc1_sleep: usdhc1grp-sleep {
+       pinctrl_usdhc1_sleep: usdhc1-sleep-grp {
                fsl,pins = <
                        MX6UL_PAD_SD1_CMD__GPIO2_IO16           0x3000
                        MX6UL_PAD_SD1_CLK__GPIO2_IO17           0x3000
@@ -250,7 +250,7 @@
                >;
        };
 
-       pinctrl_wifibt_ctrl_sleep: wifibt-ctrl-grp-sleep {
+       pinctrl_wifibt_ctrl_sleep: wifibt-ctrl-sleep-grp {
                fsl,pins = <
                        MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00      0x3000
                        MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09      0x3000

diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-geam.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-geam.dts
index 601d89b904cdfb1c704c2e5ae4e4bf7bdd435b6b..2a6bb5ff808add0d3648480061e136e1050a1ccf 100644 (file)
--- a/arch/arm/boot/dts/nxp/imx/imx6ul-geam.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx6ul-geam.dts
@@ -410,7 +410,7 @@
                >;
        };
 
-       pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+       pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp {
                fsl,pins = <
                        MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170b9
                        MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100b9
@@ -421,7 +421,7 @@
                >;
        };
 
-       pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+       pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp {
                fsl,pins = <
                        MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170f9
                        MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100f9

diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-isiot.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-isiot.dtsi
index ee86c36205f9554dd1c8b5b853df3742ab9ae426..118df2a457c952cc1479e9fe17711a7a44c3d123 100644 (file)
--- a/arch/arm/boot/dts/nxp/imx/imx6ul-isiot.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6ul-isiot.dtsi
@@ -346,7 +346,7 @@
                >;
        };
 
-       pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+       pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp {
                fsl,pins = <
                        MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170b9
                        MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100b9
@@ -357,7 +357,7 @@
                >;
        };
 
-       pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+       pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp {
                fsl,pins = <
                        MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170f9
                        MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100f9

diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-kontron-bl-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-kontron-bl-common.dtsi
index d8f7877349c98fdeb8c211a719c303b978e57cd0..29d2f86d5e34a74d6cc498f25b35da70a5f72c0d 100644 (file)
--- a/arch/arm/boot/dts/nxp/imx/imx6ul-kontron-bl-common.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6ul-kontron-bl-common.dtsi
@@ -351,7 +351,7 @@
                >;
        };
 
-       pinctrl_usbotg1: usbotg1 {
+       pinctrl_usbotg1: usbotg1grp {
                fsl,pins = <
                        MX6UL_PAD_GPIO1_IO04__GPIO1_IO04        0x1b0b0
                >;

diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-liteboard.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-liteboard.dts
index 1d863a16bcf09c54ed76650edf2591b1be56ac52..5e62272acfba89af5a2d85aae8eb3b8ad4fb67df 100644 (file)
--- a/arch/arm/boot/dts/nxp/imx/imx6ul-liteboard.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx6ul-liteboard.dts
@@ -100,7 +100,7 @@
                >;
        };
 
-       pinctrl_usb_otg1_vbus: usb-otg1-vbus {
+       pinctrl_usb_otg1_vbus: usb-otg1-vbus-grp {
                fsl,pins = <
                        MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08    0x79
                >;

diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-phytec-segin-peb-wlbt-05.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-phytec-segin-peb-wlbt-05.dtsi
index 04477fd4b9a98d15b2f39adac0466202f2014f41..4a45fb784ff770365913fb7d6d10c7530e67bf08 100644 (file)
--- a/arch/arm/boot/dts/nxp/imx/imx6ul-phytec-segin-peb-wlbt-05.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6ul-phytec-segin-peb-wlbt-05.dtsi
@@ -31,7 +31,7 @@
                >;
        };
 
-       pinctrl_uart2_bt: uart2grp-bt {
+       pinctrl_uart2_bt: uart2-bt-grp {
                fsl,pins = <
                        MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX   0x17059
                        MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX   0x17059
@@ -40,7 +40,7 @@
                >;
        };
 
-       pinctrl_usdhc2_wl: usdhc2grp-wl {
+       pinctrl_usdhc2_wl: usdhc2-wl-grp {
                fsl,pins = <
                        MX6UL_PAD_LCD_DATA18__USDHC2_CMD    0x10051
                        MX6UL_PAD_LCD_DATA19__USDHC2_CLK    0x10061

diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-phytec-segin.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-phytec-segin.dtsi
index 38ea4dcfa2281d23f069e71c4ff9b2fe93f97423..bef5eb38a90d3dbff6a2aad9231d520b0c499333 100644 (file)
--- a/arch/arm/boot/dts/nxp/imx/imx6ul-phytec-segin.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6ul-phytec-segin.dtsi
@@ -219,7 +219,7 @@
                >;
        };
 
-       pinctrl_flexcan1: flexcan1 {
+       pinctrl_flexcan1: flexcan1grp {
                fsl,pins = <
                        MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX      0x0b0b0
                        MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX      0x0b0b0
@@ -275,7 +275,7 @@
                >;
        };
 
-       pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+       pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp {
                fsl,pins = <
                        MX6UL_PAD_SD1_CMD__USDHC1_CMD           0x170b9
                        MX6UL_PAD_SD1_CLK__USDHC1_CLK           0x100b9
@@ -286,7 +286,7 @@
                >;
        };
 
-       pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+       pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp {
                fsl,pins = <
                        MX6UL_PAD_SD1_CMD__USDHC1_CMD           0x170f9
                        MX6UL_PAD_SD1_CLK__USDHC1_CLK           0x100f9

diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul-common.dtsi
index 57e647fc3237426c9fddacdf24b1ad58d6da2419..c9c0794f01a2b8c88c2a049204fec1c04d2edc76 100644 (file)
--- a/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul-common.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul-common.dtsi
@@ -202,7 +202,7 @@
                >;
        };
 
-       pinctrl_pmic: pmic {
+       pinctrl_pmic: pmicgrp {
                fsl,pins = <
                        /* PMIC irq */
                        MX6UL_PAD_CSI_DATA03__GPIO4_IO24        0x1b099

diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul-mainboard.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul-mainboard.dts
index ef76ece21010b1493cd20524b4c042406def2253..20c810a81403a31b91bed018d9ad36d935adb5de 100644 (file)
--- a/arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul-mainboard.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul-mainboard.dts
@@ -198,7 +198,7 @@
                >;
        };
 
-       pinctrl_disp0_3: disp0grp-3 {
+       pinctrl_disp0_3: disp0-3-grp {
                fsl,pins = <
                        MX6UL_PAD_LCD_CLK__LCDIF_CLK            0x10 /* LSCLK */
                        MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE      0x10 /* OE_ACD */

diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul.dtsi
index 2567fa52f29bcf9cd5047a06da756ac36cfa7349..278120404d3175683c90a81dc1581d1e2845aa12 100644 (file)
--- a/arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul.dtsi
@@ -584,7 +584,7 @@
                >;
        };
 
-       pinctrl_disp0_1: disp0grp-1 {
+       pinctrl_disp0_1: disp0-1-grp {
                fsl,pins = <
                        MX6UL_PAD_LCD_CLK__LCDIF_CLK            0x10 /* LSCLK */
                        MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE      0x10 /* OE_ACD */
@@ -617,7 +617,7 @@
                >;
        };
 
-       pinctrl_disp0_2: disp0grp-2 {
+       pinctrl_disp0_2: disp0-2-grp {
                fsl,pins = <
                        MX6UL_PAD_LCD_CLK__LCDIF_CLK            0x10 /* LSCLK */
                        MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE      0x10 /* OE_ACD */
@@ -707,25 +707,25 @@
                >;
        };
 
-       pinctrl_etnphy0_int: etnphy-intgrp-0 {
+       pinctrl_etnphy0_int: etnphy-int-0-grp {
                fsl,pins = <
                        MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05      0x0b0b0 /* ETN PHY INT */
                >;
        };
 
-       pinctrl_etnphy0_rst: etnphy-rstgrp-0 {
+       pinctrl_etnphy0_rst: etnphy-rst-0-grp {
                fsl,pins = <
                        MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06      0x0b0b0 /* ETN PHY RESET */
                >;
        };
 
-       pinctrl_etnphy1_int: etnphy-intgrp-1 {
+       pinctrl_etnphy1_int: etnphy-int-1-grp {
                fsl,pins = <
                        MX6UL_PAD_CSI_DATA06__GPIO4_IO27        0x0b0b0 /* ETN PHY INT */
                >;
        };
 
-       pinctrl_etnphy1_rst: etnphy-rstgrp-1 {
+       pinctrl_etnphy1_rst: etnphy-rst-1-grp {
                fsl,pins = <
                        MX6UL_PAD_CSI_DATA07__GPIO4_IO28        0x0b0b0 /* ETN PHY RESET */
                >;

diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-myir-mys-6ulx.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-myir-mys-6ulx.dtsi
index d03694feaf5c4a7ce4431d2b3611d344ac923571..83b9de17cee2de37c15a461ddbdc74f0aee2e34c 100644 (file)
--- a/arch/arm/boot/dts/nxp/imx/imx6ull-myir-mys-6ulx.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6ull-myir-mys-6ulx.dtsi
@@ -169,7 +169,7 @@
                >;
        };
 
-       pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+       pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp {
                fsl,pins = <
                        MX6UL_PAD_SD1_CMD__USDHC1_CMD           0x170b9
                        MX6UL_PAD_SD1_CLK__USDHC1_CLK           0x100b9
@@ -180,7 +180,7 @@
                >;
        };
 
-       pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+       pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp {
                fsl,pins = <
                        MX6UL_PAD_SD1_CMD__USDHC1_CMD           0x170f9
                        MX6UL_PAD_SD1_CLK__USDHC1_CLK           0x100f9
@@ -206,7 +206,7 @@
                >;
        };
 
-       pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+       pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp {
                fsl,pins = <
                        MX6UL_PAD_NAND_RE_B__USDHC2_CLK         0x100b9
                        MX6UL_PAD_NAND_WE_B__USDHC2_CMD         0x170b9
@@ -221,7 +221,7 @@
                >;
        };
 
-       pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+       pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp {
                fsl,pins = <
                        MX6UL_PAD_NAND_RE_B__USDHC2_CLK         0x100f9
                        MX6UL_PAD_NAND_WE_B__USDHC2_CMD         0x170f9

diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-seeed-npi-dev-board.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-seeed-npi-dev-board.dtsi
index 50654dbf62e02ce1ba80f1a9ac32887e08b16b13..28fddbcdc55e70319a44f197f8352061d5de6e1d 100644 (file)
--- a/arch/arm/boot/dts/nxp/imx/imx6ull-seeed-npi-dev-board.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6ull-seeed-npi-dev-board.dtsi
@@ -323,7 +323,7 @@
                >;
        };
 
-       pinctrl_reg_vmmc: usdhc1regvmmc {
+       pinctrl_reg_vmmc: usdhc1regvmmc-grp {
                fsl,pins = <
                        MX6UL_PAD_GPIO1_IO09__GPIO1_IO09        0x17059
                >;
@@ -394,7 +394,7 @@
                >;
        };
 
-       pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+       pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp {
                fsl,pins = <
                        MX6UL_PAD_SD1_CMD__USDHC1_CMD           0x170b9
                        MX6UL_PAD_SD1_CLK__USDHC1_CLK           0x100b9
@@ -405,7 +405,7 @@
                >;
        };
 
-       pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+       pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp {
                fsl,pins = <
                        MX6UL_PAD_SD1_CMD__USDHC1_CMD           0x170f9
                        MX6UL_PAD_SD1_CLK__USDHC1_CLK           0x100f9
@@ -416,7 +416,7 @@
                >;
        };
 
-       pinctrl_usdhc1_cd: usdhc1cd {
+       pinctrl_usdhc1_cd: usdhc1cd-grp {
                fsl,pins = <
                        MX6UL_PAD_UART1_RTS_B__GPIO1_IO19       0x17059
                >;

diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-seeed-npi.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-seeed-npi.dtsi
index f5ad6b5c1ad01c57d003bb6891b7724b3637f594..278152875f8e6cf1342ff73464e0a89fafbe8dca 100644 (file)
--- a/arch/arm/boot/dts/nxp/imx/imx6ull-seeed-npi.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6ull-seeed-npi.dtsi
@@ -102,7 +102,7 @@
                >;
        };
 
-       pinctrl_reg_vqmmc: usdhc1regvqmmc {
+       pinctrl_reg_vqmmc: usdhc1regvqmmcgrp {
                fsl,pins = <
                        MX6UL_PAD_GPIO1_IO05__GPIO1_IO05        0x17059
                >;
@@ -123,7 +123,7 @@
                >;
        };
 
-       pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+       pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp {
                fsl,pins = <
                        MX6UL_PAD_NAND_RE_B__USDHC2_CLK         0x100b9
                        MX6UL_PAD_NAND_WE_B__USDHC2_CMD         0x170b9
@@ -138,7 +138,7 @@
                >;
        };
 
-       pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+       pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp {
                fsl,pins = <
                        MX6UL_PAD_NAND_RE_B__USDHC2_CLK         0x100f9
                        MX6UL_PAD_NAND_WE_B__USDHC2_CMD         0x170f9

diff --git a/arch/arm/boot/dts/nxp/imx/imx6ulz-bsh-smm-m2.dts b/arch/arm/boot/dts/nxp/imx/imx6ulz-bsh-smm-m2.dts
index c92e4e2f6ab9ca064ddb774b96dd9e62c1b1df45..6159ed70d96616053f16426f3fc9f19b468bd408 100644 (file)
--- a/arch/arm/boot/dts/nxp/imx/imx6ulz-bsh-smm-m2.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx6ulz-bsh-smm-m2.dts
@@ -94,7 +94,7 @@
 };
 
 &iomuxc {
-       pinctrl_gpmi_nand: gpmi-nand {
+       pinctrl_gpmi_nand: gpminandgrp {
                fsl,pins = <
                        MX6UL_PAD_NAND_CLE__RAWNAND_CLE         0xb0b1
                        MX6UL_PAD_NAND_ALE__RAWNAND_ALE         0xb0b1

diff --git a/arch/arm/boot/dts/nxp/imx/mba6ulx.dtsi b/arch/arm/boot/dts/nxp/imx/mba6ulx.dtsi
index e78d0a7d8cd28cf3637cd5d3ab0a45089e994813..941d9860218e96673048381f8aab8f30707d9b8d 100644 (file)
--- a/arch/arm/boot/dts/nxp/imx/mba6ulx.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/mba6ulx.dtsi
@@ -505,7 +505,7 @@
                >;
        };
 
-       pinctrl_uart6dte: uart6dte {
+       pinctrl_uart6dte: uart6dtegrp {
                fsl,pins = <
                        MX6UL_PAD_CSI_PIXCLK__UART6_DTE_TX      0x1b0b1
                        MX6UL_PAD_CSI_MCLK__UART6_DTE_RX        0x1b0b1
@@ -537,7 +537,7 @@
                >;
        };
 
-       pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+       pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp {
                fsl,pins = <
                        MX6UL_PAD_SD1_CLK__USDHC1_CLK           0x00017069
                        MX6UL_PAD_SD1_CMD__USDHC1_CMD           0x000170b9
@@ -552,7 +552,7 @@
                >;
        };
 
-       pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+       pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp {
                fsl,pins = <
                        MX6UL_PAD_SD1_CLK__USDHC1_CLK           0x00017069
                        MX6UL_PAD_SD1_CMD__USDHC1_CMD           0x000170f9