bool                            debug_disable_soft_recovery;
        bool                            debug_use_vram_fw_buf;
        bool                            debug_enable_ras_aca;
+       bool                            debug_exp_resets;
 
        bool                            enforce_isolation[MAX_XCP];
        /* Added this mutex for cleaner shader isolation between GFX and compute processes */
 
        AMDGPU_DEBUG_DISABLE_GPU_SOFT_RECOVERY = BIT(2),
        AMDGPU_DEBUG_USE_VRAM_FW_BUF = BIT(3),
        AMDGPU_DEBUG_ENABLE_RAS_ACA = BIT(4),
+       AMDGPU_DEBUG_ENABLE_EXP_RESETS = BIT(5),
 };
 
 unsigned int amdgpu_vram_limit = UINT_MAX;
                pr_info("debug: enable RAS ACA\n");
                adev->debug_enable_ras_aca = true;
        }
+
+       if (amdgpu_debug_mask & AMDGPU_DEBUG_ENABLE_EXP_RESETS) {
+               pr_info("debug: enable experimental reset features\n");
+               adev->debug_exp_resets = true;
+       }
 }
 
 static unsigned long amdgpu_fix_asic_type(struct pci_dev *pdev, unsigned long flags)