* Advent Networks, Inc. <http://www.adventnetworks.com>
* Jay Monkman <jtm@smoothsmoothie.com>
*
- * Configuation settings for the R&S Protocol Board board.
+ * Configuation settings for the WindRiver SBC8260 board.
+ * See http://www.windriver.com/products/html/sbc8260.html
*
* See file CREDITS for list of people who contributed to this
* project.
#ifndef __CONFIG_H
#define __CONFIG_H
+/* Enable debug prints */
+#undef DEBUG /* General debug */
+#undef DEBUG_BOOTP_EXT /* Debug received vendor fields */
/*****************************************************************************
*
*/
#define CFG_LED_BASE 0xa0000000
+
+/*
+ * SBC8260 with 16 MB DIMM:
+ *
+ * 0x0000 0000 Exception Vector code, 8k
+ * :
+ * 0x0000 1FFF
+ * 0x0000 2000 Free for Application Use
+ * :
+ * :
+ *
+ * :
+ * :
+ * 0x00F5 FF30 Monitor Stack (Growing downward)
+ * Monitor Stack Buffer (0x80)
+ * 0x00F5 FFB0 Board Info Data
+ * 0x00F6 0000 Malloc Arena
+ * : CFG_ENV_SECT_SIZE, 256k
+ * : CFG_MALLOC_LEN, 128k
+ * 0x00FC 0000 RAM Copy of Monitor Code
+ * : CFG_MONITOR_LEN, 256k
+ * 0x00FF FFFF [End of RAM], CFG_SDRAM_SIZE - 1
+ */
+
+/*
+ * SBC8260 with 64 MB DIMM:
+ *
+ * 0x0000 0000 Exception Vector code, 8k
+ * :
+ * 0x0000 1FFF
+ * 0x0000 2000 Free for Application Use
+ * :
+ * :
+ *
+ * :
+ * :
+ * 0x03F5 FF30 Monitor Stack (Growing downward)
+ * Monitor Stack Buffer (0x80)
+ * 0x03F5 FFB0 Board Info Data
+ * 0x03F6 0000 Malloc Arena
+ * : CFG_ENV_SECT_SIZE, 256k
+ * : CFG_MALLOC_LEN, 128k
+ * 0x03FC 0000 RAM Copy of Monitor Code
+ * : CFG_MONITOR_LEN, 256k
+ * 0x03FF FFFF [End of RAM], CFG_SDRAM_SIZE - 1
+ */
+
+
/*
* select serial console configuration
*
#define CFG_LOAD_ADDR 0x140000 /* default load address */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
-#define CFG_MEMTEST_START CFG_LOAD_ADDR
- /* memtest works on the load */
- /* addr to the end of the DRAM */
+#define CFG_MEMTEST_START 0x2000 /* memtest works from the end of */
+ /* the exception vector table */
+ /* to the end of the DRAM */
/* less monitor and malloc area */
#define CFG_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */
#define CFG_MEM_END_USAGE ( CFG_MONITOR_LEN \
#define CFG_RCCR 0
/*
- * Init Memory Controller:
+ * Initialize Memory Controller:
*
* Bank Bus Machine PortSz Device
* ---- --- ------- ------ ------
* 0 60x GPCM 32 bit FLASH (SIMM - 4MB) *
- * 1 60x GPCM 32 bit FLASH (SIMM - unused)
- * 2 60x SDRAM 64 bit SDRAM (DIMM - 16MB)
+ * 1 60x GPCM 32 bit FLASH (SIMM - Unused)
+ * 2 60x SDRAM 64 bit SDRAM (DIMM - 16MB or 64MB)
* 3 60x SDRAM 64 bit SDRAM (DIMM - Unused)
* 4 Local SDRAM 32 bit SDRAM (on board - 4MB)
* 5 60x GPCM 8 bit EEPROM (8KB)
*
*/
+/*-----------------------------------------------------------------------
+ * BR0,BR1 - Base Register
+ * Ref: Section 10.3.1 on page 10-14
+ * OR0,OR1 - Option Register
+ * Ref: Section 10.3.2 on page 10-18
+ *-----------------------------------------------------------------------
+ */
+
/* Bank 0,1 - FLASH SIMM
*
* This expects the FLASH SIMM to be connected to *CS0
* It consists of 4 AM29F080B parts.
*
- * For the 4 MB SIMM, *CS1 is unused.
+ * Note: For the 4 MB SIMM, *CS1 is unused.
+ */
+
+/* BR0 is configured as follows:
+ *
+ * - Base address of 0x40000000
+ * - 32 bit port size
+ * - Data errors checking is disabled
+ * - Read and write access
+ * - GPCM 60x bus
+ * - Access are handled by the memory controller according to MSEL
+ * - Not used for atomic operations
+ * - No data pipelining is done
+ * - Valid
*/
#define CFG_BR0_PRELIM ((CFG_FLASH0_BASE & BRx_BA_MSK) |\
BRx_PS_32 |\
BRx_MS_GPCM_P |\
BRx_V)
+/* OR0 is configured as follows:
+ *
+ * - 4 MB
+ * - *BCTL0 is asserted upon access to the current memory bank
+ * - *CW / *WE are negated a quarter of a clock earlier
+ * - *CS is output at the same time as the address lines
+ * - Uses a clock cycle length of 5
+ * - *PSDVAL is generated internally by the memory controller
+ * unless *GTA is asserted earlier externally.
+ * - Relaxed timing is generated by the GPCM for accesses
+ * initiated to this memory region.
+ * - One idle clock is inserted between a read access from the
+ * current bank and the next access.
+ */
#define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH0_SIZE) |\
ORxG_CSNT |\
ORxG_ACS_DIV1 |\
ORxG_SCY_5_CLK |\
- ORxG_EHTR |\
- ORxG_TRLX)
+ ORxG_TRLX |\
+ ORxG_EHTR)
+
+/*-----------------------------------------------------------------------
+ * BR2,BR3 - Base Register
+ * Ref: Section 10.3.1 on page 10-14
+ * OR2,OR3 - Option Register
+ * Ref: Section 10.3.2 on page 10-16
+ *-----------------------------------------------------------------------
+ */
/* Bank 2,3 - SDRAM DIMM
+ *
+ * 16MB DIMM: P/N
+ * 64MB DIMM: P/N 1W-8864X8-4-P1-EST
*
- * This relies on the 16 MB SDRAM DIMM.
- *
- * *CS3 is unused for this DIMM
- *
- * NOTE: This works with the DIMM that came with my (Jay Monkman's)
- * SCB8260. It's EST part number appears to be:
- * 1W-8864X8-4-P1-EST
- * The DIMM has 8 IBM 0364804CT3C 8Mx8 SDRAM chips.
- * Hmmm, 8 8Mx8 chips = 64 MB not 16. Well, we'll
- * pretend it's only 16 MB.
+ * Note: *CS3 is unused for this DIMM
*/
+/* With a 16 MB or 64 MB DIMM, the BR2 is configured as follows:
+ *
+ * - Base address of 0x00000000
+ * - 64 bit port size (60x bus only)
+ * - Data errors checking is disabled
+ * - Read and write access
+ * - SDRAM 60x bus
+ * - Access are handled by the memory controller according to MSEL
+ * - Not used for atomic operations
+ * - No data pipelining is done
+ * - Valid
+ */
#define CFG_BR2_PRELIM ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\
BRx_PS_64 |\
BRx_MS_SDRAM_P |\
BRx_V)
+/* With a 16 MB DIMM, the OR2 is configured as follows:
+ *
+ * - 16 MB
+ * - 2 internal banks per device
+ * - Row start address bit is A9 with PSDMR[PBI] = 0
+ * - 11 row address lines
+ * - Back-to-back page mode
+ * - Internal bank interleaving within save device enabled
+ */
+#if (CFG_SDRAM0_SIZE == 16)
#define CFG_OR2_PRELIM (MEG_TO_AM(CFG_SDRAM0_SIZE) |\
ORxS_BPD_2 |\
ORxS_ROWST_PBI0_A9 |\
ORxS_NUMR_11)
+#endif
+
+/* With a 64 MB DIMM, the OR2 is configured as follows:
+ *
+ * - 64 MB
+ * - 4 internal banks per device
+ * - Row start address bit is A8 with PSDMR[PBI] = 0
+ * - 12 row address lines
+ * - Back-to-back page mode
+ * - Internal bank interleaving within save device enabled
+ */
+#if (CFG_SDRAM0_SIZE == 64)
+#define CFG_OR2_PRELIM (MEG_TO_AM(CFG_SDRAM0_SIZE) |\
+ ORxS_BPD_4 |\
+ ORxS_ROWST_PBI0_A8 |\
+ ORxS_NUMR_12)
+#endif
+
+/*-----------------------------------------------------------------------
+ * PSDMR - 60x Bus SDRAM Mode Register
+ * Ref: Section 10.3.3 on page 10-21
+ *-----------------------------------------------------------------------
+ */
-/* The 60x Bus SDRAM Mode Register (PSDMR) is set as follows:
+#if (CFG_SDRAM0_SIZE == 16)
+/* With a 16 MB DIMM, the PSDMR is configured as follows:
*
- * Page Based Interleaving, Refresh Enable, Address Multiplexing where A5
- * is output on A14 pin (A6 on A15, and so on), use address pins A16-A18
- * as bank select, A9 is output on SDA10 during an ACTIVATE command,
- * earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
- * earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
- * is 3 clocks, earliest timing for READ/WRITE command after ACTIVATE
- * command is 2 clocks, earliest timing for PRECHARGE after last data
- * was read is 1 clock, earliest timing for PRECHARGE after last data
- * was written is 1 clock, CAS Latency is 2.
+ * - Page Based Interleaving,
+ * - Refresh Enable,
+ * - Address Multiplexing where A5 is output on A14 pin
+ * (A6 on A15, and so on),
+ * - use address pins A16-A18 as bank select,
+ * - A9 is output on SDA10 during an ACTIVATE command,
+ * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
+ * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
+ * is 3 clocks,
+ * - earliest timing for READ/WRITE command after ACTIVATE command is
+ * 2 clocks,
+ * - earliest timing for PRECHARGE after last data was read is 1 clock,
+ * - earliest timing for PRECHARGE after last data was written is 1 clock,
+ * - CAS Latency is 2.
*/
#define CFG_PSDMR (PSDMR_RFEN |\
PSDMR_SDAM_A14_IS_A5 |\
PSDMR_LDOTOPRE_1C |\
PSDMR_WRC_1C |\
PSDMR_CL_2)
+#endif
+
+#if (CFG_SDRAM0_SIZE == 64)
+/* With a 64 MB DIMM, the PSDMR is configured as follows:
+ *
+ * - Page Based Interleaving,
+ * - Refresh Enable,
+ * - Address Multiplexing where A5 is output on A14 pin
+ * (A6 on A15, and so on),
+ * - use address pins A14-A16 as bank select,
+ * - A9 is output on SDA10 during an ACTIVATE command,
+ * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
+ * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
+ * is 3 clocks,
+ * - earliest timing for READ/WRITE command after ACTIVATE command is
+ * 2 clocks,
+ * - earliest timing for PRECHARGE after last data was read is 1 clock,
+ * - earliest timing for PRECHARGE after last data was written is 1 clock,
+ * - CAS Latency is 2.
+ */
+#define CFG_PSDMR (PSDMR_RFEN |\
+ PSDMR_SDAM_A14_IS_A5 |\
+ PSDMR_BSMA_A14_A16 |\
+ PSDMR_SDA10_PBI0_A9 |\
+ PSDMR_RFRC_7_CLK |\
+ PSDMR_PRETOACT_3W |\
+ PSDMR_ACTTORW_2W |\
+ PSDMR_LDOTOPRE_1C |\
+ PSDMR_WRC_1C |\
+ PSDMR_CL_2)
+#endif
#define CFG_PSRT 0x0e
#define CFG_MPTPR ( (0x32 << MPTPR_PTP_SHIFT) & MPTPR_PTP_MSK)
* This is not implemented yet.
*/
+/*-----------------------------------------------------------------------
+ * BR6 - Base Register
+ * Ref: Section 10.3.1 on page 10-14
+ * OR6 - Option Register
+ * Ref: Section 10.3.2 on page 10-18
+ *-----------------------------------------------------------------------
+ */
/* Bank 6 - On board FLASH
*
* It consists of 1 AM29F016A part.
*/
#if (defined(CFG_FLASH1_BASE) && defined(CFG_FLASH1_SIZE))
+
+/* BR6 is configured as follows:
+ *
+ * - Base address of 0x60000000
+ * - 8 bit port size
+ * - Data errors checking is disabled
+ * - Read and write access
+ * - GPCM 60x bus
+ * - Access are handled by the memory controller according to MSEL
+ * - Not used for atomic operations
+ * - No data pipelining is done
+ * - Valid
+ */
# define CFG_BR6_PRELIM ((CFG_FLASH1_BASE & BRx_BA_MSK) |\
BRx_PS_8 |\
BRx_MS_GPCM_P |\
BRx_V)
+/* OR6 is configured as follows:
+ *
+ * - 2 MB
+ * - *BCTL0 is asserted upon access to the current memory bank
+ * - *CW / *WE are negated a quarter of a clock earlier
+ * - *CS is output at the same time as the address lines
+ * - Uses a clock cycle length of 5
+ * - *PSDVAL is generated internally by the memory controller
+ * unless *GTA is asserted earlier externally.
+ * - Relaxed timing is generated by the GPCM for accesses
+ * initiated to this memory region.
+ * - One idle clock is inserted between a read access from the
+ * current bank and the next access.
+ */
# define CFG_OR6_PRELIM (MEG_TO_AM(CFG_FLASH1_SIZE) |\
ORxG_CSNT |\
ORxG_ACS_DIV1 |\
ORxG_SCY_5_CLK |\
- ORxG_EHTR |\
- ORxG_TRLX)
+ ORxG_TRLX |\
+ ORxG_EHTR)
#endif /* (defined(CFG_FLASH1_BASE) && defined(CFG_FLASH1_SIZE)) */
+/*-----------------------------------------------------------------------
+ * BR7 - Base Register
+ * Ref: Section 10.3.1 on page 10-14
+ * OR7 - Option Register
+ * Ref: Section 10.3.2 on page 10-18
+ *-----------------------------------------------------------------------
+ */
+
/* Bank 7 - LEDs and switches
*
- * LEDs are at 0x00001 (write only)
- * swithes are at 0x00001 (read only)
+ * LEDs are at 0x00001 (write only)
+ * switches are at 0x00001 (read only)
*/
#ifdef CFG_LED_BASE
+
+/* BR7 is configured as follows:
+ *
+ * - Base address of 0xA0000000
+ * - 8 bit port size
+ * - Data errors checking is disabled
+ * - Read and write access
+ * - GPCM 60x bus
+ * - Access are handled by the memory controller according to MSEL
+ * - Not used for atomic operations
+ * - No data pipelining is done
+ * - Valid
+ */
# define CFG_BR7_PRELIM ((CFG_LED_BASE & BRx_BA_MSK) |\
BRx_PS_8 |\
BRx_MS_GPCM_P |\
BRx_V)
+/* OR7 is configured as follows:
+ *
+ * - 1 byte
+ * - *BCTL0 is asserted upon access to the current memory bank
+ * - *CW / *WE are negated a quarter of a clock earlier
+ * - *CS is output at the same time as the address lines
+ * - Uses a clock cycle length of 15
+ * - *PSDVAL is generated internally by the memory controller
+ * unless *GTA is asserted earlier externally.
+ * - Relaxed timing is generated by the GPCM for accesses
+ * initiated to this memory region.
+ * - One idle clock is inserted between a read access from the
+ * current bank and the next access.
+ */
# define CFG_OR7_PRELIM (ORxG_AM_MSK |\
ORxG_CSNT |\
ORxG_ACS_DIV1 |\
ORxG_SCY_15_CLK |\
- ORxG_EHTR |\
- ORxG_TRLX)
+ ORxG_TRLX |\
+ ORxG_EHTR)
#endif /* CFG_LED_BASE */
/*
projects / users / rw / ppcboot.git / commitdiff