net: dsa: qca8k: Enable delay for RGMII_ID mode

RGMII_ID specifies that we should have internal delay, so resurrect the
delay addition routine but under the RGMII_ID mode.

Fixes: 40269aa9f40a ("net: dsa: qca8k: disable delay for RGMII mode")
Tested-by: Michal Vokáč <michal.vokac@ysoft.com>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c
index a4b6cda380169868d7843fc0bf3af6b53ce57f1b..195a8a87b98411ef06d11a29575962fe0ce03830 100644 (file)
--- a/drivers/net/dsa/qca8k.c
+++ b/drivers/net/dsa/qca8k.c
@@ -443,6 +443,18 @@ qca8k_set_pad_ctrl(struct qca8k_priv *priv, int port, int mode)
                val = QCA8K_PORT_PAD_RGMII_EN;
                qca8k_write(priv, reg, val);
                break;
+       case PHY_INTERFACE_MODE_RGMII_ID:
+               /* RGMII_ID needs internal delay. This is enabled through
+                * PORT5_PAD_CTRL for all ports, rather than individual port
+                * registers
+                */
+               qca8k_write(priv, reg,
+                           QCA8K_PORT_PAD_RGMII_EN |
+                           QCA8K_PORT_PAD_RGMII_TX_DELAY(QCA8K_MAX_DELAY) |
+                           QCA8K_PORT_PAD_RGMII_RX_DELAY(QCA8K_MAX_DELAY));
+               qca8k_write(priv, QCA8K_REG_PORT5_PAD_CTRL,
+                           QCA8K_PORT_PAD_RGMII_RX_DELAY_EN);
+               break;
        case PHY_INTERFACE_MODE_SGMII:
                qca8k_write(priv, reg, QCA8K_PORT_PAD_SGMII_EN);
                break;

diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h
index 613fe5c50236c50cfbc6659b5a7d895b21409ec9..d146e54c8a6c615045ff18b31b413fba08365221 100644 (file)
--- a/drivers/net/dsa/qca8k.h
+++ b/drivers/net/dsa/qca8k.h
@@ -40,6 +40,7 @@
                                                ((0x8 + (x & 0x3)) << 22)
 #define   QCA8K_PORT_PAD_RGMII_RX_DELAY(x)             \
                                                ((0x10 + (x & 0x3)) << 20)
+#define   QCA8K_MAX_DELAY                              3
 #define   QCA8K_PORT_PAD_RGMII_RX_DELAY_EN             BIT(24)
 #define   QCA8K_PORT_PAD_SGMII_EN                      BIT(7)
 #define QCA8K_REG_MODULE_EN                            0x030