arm64: dts: renesas: r9a07g043u: Add FCPVD node

Add FCPVD node to RZ/G2UL SoC DTSI.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20240805131709.101679-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
index 20fb5e41c5988c65d16485617f35466a8d8020c8..4cfcef60680cb52865380842eb780c13d803d4c5 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
@@ -129,6 +129,17 @@
                };
        };
 
+       fcpvd: fcp@10880000 {
+               compatible = "renesas,r9a07g043u-fcpvd", "renesas,fcpv";
+               reg = <0 0x10880000 0 0x10000>;
+               clocks = <&cpg CPG_MOD R9A07G043_LCDC_CLK_A>,
+                        <&cpg CPG_MOD R9A07G043_LCDC_CLK_P>,
+                        <&cpg CPG_MOD R9A07G043_LCDC_CLK_D>;
+               clock-names = "aclk", "pclk", "vclk";
+               power-domains = <&cpg>;
+               resets = <&cpg R9A07G043_LCDC_RESET_N>;
+       };
+
        irqc: interrupt-controller@110a0000 {
                compatible = "renesas,r9a07g043u-irqc",
                             "renesas,rzg2l-irqc";