arm64: dts: renesas: rzg3s-smarc-som: Add versa3 clock generator node

Add versa3 clock generator node. It provides the clocks for the Ethernet
PHY, PCIe, audio devices.

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Link: https://lore.kernel.org/20241210170953.2936724-22-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
index 4ee91ea05261e1765d9660e00b7e005d84faef3c..5117de3c8c4b14ec19962f00616eedb92aaeebcf 100644 (file)
--- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
@@ -87,6 +87,12 @@
                gpios = <&pinctrl RZG2L_GPIO(8, 1) GPIO_ACTIVE_HIGH>;
                enable-active-high;
        };
+
+       x3_clk: x3-clock {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <24000000>;
+       };
 };
 
 &adc {
@@ -151,6 +157,30 @@
 
 &i2c1 {
        status = "okay";
+
+       versa3: clock-generator@68 {
+               compatible = "renesas,5l35023";
+               reg = <0x68>;
+               clocks = <&x3_clk>;
+               #clock-cells = <1>;
+               assigned-clocks = <&versa3 0>,
+                                 <&versa3 1>,
+                                 <&versa3 2>,
+                                 <&versa3 3>,
+                                 <&versa3 4>,
+                                 <&versa3 5>;
+               assigned-clock-rates = <24000000>,
+                                      <12288000>,
+                                      <11289600>,
+                                      <25000000>,
+                                      <100000000>,
+                                      <100000000>;
+               renesas,settings = [
+                 80 00 11 19 4c 42 dc 2f 06 7d 20 1a 5f 1e f2 27
+                 00 40 00 00 00 00 00 00 06 0c 19 02 3f f0 90 86
+                 a0 80 30 30 9c
+               ];
+       };
 };
 
 #if SW_CONFIG2 == SW_ON