Initialize the emulated EL1 physical timer with the default irq number.
Signed-off-by: Jintack Lim <jintack@cs.columbia.edu>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
        .usr_regs.ARM_cpsr = SVC_MODE | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT,
 };
 
+static const struct kvm_irq_level cortexa_ptimer_irq = {
+       { .irq = 30 },
+       .level = 1,
+};
+
 static const struct kvm_irq_level cortexa_vtimer_irq = {
        { .irq = 27 },
        .level = 1,
 {
        struct kvm_regs *reset_regs;
        const struct kvm_irq_level *cpu_vtimer_irq;
+       const struct kvm_irq_level *cpu_ptimer_irq;
 
        switch (vcpu->arch.target) {
        case KVM_ARM_TARGET_CORTEX_A7:
                reset_regs = &cortexa_regs_reset;
                vcpu->arch.midr = read_cpuid_id();
                cpu_vtimer_irq = &cortexa_vtimer_irq;
+               cpu_ptimer_irq = &cortexa_ptimer_irq;
                break;
        default:
                return -ENODEV;
        kvm_reset_coprocs(vcpu);
 
        /* Reset arch_timer context */
-       return kvm_timer_vcpu_reset(vcpu, cpu_vtimer_irq);
+       return kvm_timer_vcpu_reset(vcpu, cpu_vtimer_irq, cpu_ptimer_irq);
 }
 
                        COMPAT_PSR_I_BIT | COMPAT_PSR_F_BIT),
 };
 
+static const struct kvm_irq_level default_ptimer_irq = {
+       .irq    = 30,
+       .level  = 1,
+};
+
 static const struct kvm_irq_level default_vtimer_irq = {
        .irq    = 27,
        .level  = 1,
 int kvm_reset_vcpu(struct kvm_vcpu *vcpu)
 {
        const struct kvm_irq_level *cpu_vtimer_irq;
+       const struct kvm_irq_level *cpu_ptimer_irq;
        const struct kvm_regs *cpu_reset;
 
        switch (vcpu->arch.target) {
                }
 
                cpu_vtimer_irq = &default_vtimer_irq;
+               cpu_ptimer_irq = &default_ptimer_irq;
                break;
        }
 
        kvm_pmu_vcpu_reset(vcpu);
 
        /* Reset timer */
-       return kvm_timer_vcpu_reset(vcpu, cpu_vtimer_irq);
+       return kvm_timer_vcpu_reset(vcpu, cpu_vtimer_irq, cpu_ptimer_irq);
 }
 
 int kvm_timer_hyp_init(void);
 int kvm_timer_enable(struct kvm_vcpu *vcpu);
 int kvm_timer_vcpu_reset(struct kvm_vcpu *vcpu,
-                        const struct kvm_irq_level *irq);
+                        const struct kvm_irq_level *virt_irq,
+                        const struct kvm_irq_level *phys_irq);
 void kvm_timer_vcpu_init(struct kvm_vcpu *vcpu);
 void kvm_timer_flush_hwstate(struct kvm_vcpu *vcpu);
 void kvm_timer_sync_hwstate(struct kvm_vcpu *vcpu);
 
 }
 
 int kvm_timer_vcpu_reset(struct kvm_vcpu *vcpu,
-                        const struct kvm_irq_level *irq)
+                        const struct kvm_irq_level *virt_irq,
+                        const struct kvm_irq_level *phys_irq)
 {
        struct arch_timer_context *vtimer = vcpu_vtimer(vcpu);
+       struct arch_timer_context *ptimer = vcpu_ptimer(vcpu);
 
        /*
         * The vcpu timer irq number cannot be determined in
         * kvm_vcpu_set_target(). To handle this, we determine
         * vcpu timer irq number when the vcpu is reset.
         */
-       vtimer->irq.irq = irq->irq;
+       vtimer->irq.irq = virt_irq->irq;
+       ptimer->irq.irq = phys_irq->irq;
 
        /*
         * The bits in CNTV_CTL are architecturally reset to UNKNOWN for ARMv8
         * the ARMv7 architecture.
         */
        vtimer->cnt_ctl = 0;
+       ptimer->cnt_ctl = 0;
        kvm_timer_update_state(vcpu);
 
        return 0;
 
        /* Synchronize cntvoff across all vtimers of a VM. */
        update_vtimer_cntvoff(vcpu, kvm_phys_timer_read());
+       vcpu_ptimer(vcpu)->cntvoff = 0;
 
        INIT_WORK(&timer->expired, kvm_timer_inject_irq_work);
        hrtimer_init(&timer->timer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS);