drm/arm/komeda: update DMA mask to 40 bits

Each layer in the DPU has a 40-bit base address register, which indicates
start of frame buffer data for that layer. Komeda driver does not set
its DMA mask, which makes it 32-bit by default which does not use
the entire available possible supported by the DPU.

Update the DMA mask to align with DPU Architecture v1.0 spec.

Signed-off-by: Amjad Ouled-Ameur <amjad.ouled-ameur@arm.com>
Signed-off-by: Faiz Abbas <faiz.abbas@arm.com>
Signed-off-by: Liviu Dudau <liviu.dudau@arm.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240219100915.192475-4-faiz.abbas@arm.com
Acked-by: Liviu Dudau <liviu.dudau@arm.com>

diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_drv.c b/drivers/gpu/drm/arm/display/komeda/komeda_drv.c
index ffdeec3b3f2eaf6a1b1156b4e18c7b71144a8ede..55c3773befde25a823f9dadc342d20bc18cc06bb 100644 (file)
--- a/drivers/gpu/drm/arm/display/komeda/komeda_drv.c
+++ b/drivers/gpu/drm/arm/display/komeda/komeda_drv.c
@@ -59,6 +59,10 @@ static int komeda_platform_probe(struct platform_device *pdev)
        struct komeda_drv *mdrv;
        int err;
 
+       err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40));
+       if (err)
+               return dev_err_probe(dev, err, "DMA mask error\n");
+
        mdrv = devm_kzalloc(dev, sizeof(*mdrv), GFP_KERNEL);
        if (!mdrv)
                return -ENOMEM;