return true;
 }
 
+static void
+ilk_dummy_write(struct drm_i915_private *dev_priv)
+{
+       /* WaIssueDummyWriteToWakeupFromRC6: Issue a dummy write to wake up the
+        * chip from rc6 before touching it for real. MI_MODE is masked, hence
+        * harmless to write 0 into. */
+       I915_WRITE_NOTRACE(MI_MODE, 0);
+}
+
 #define __i915_read(x, y) \
 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
        u##x val = 0; \
+       if (IS_GEN5(dev_priv->dev)) \
+               ilk_dummy_write(dev_priv); \
        if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
                unsigned long irqflags; \
                spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \
        if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
                __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
        } \
+       if (IS_GEN5(dev_priv->dev)) \
+               ilk_dummy_write(dev_priv); \
        if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \
                write##y(val, dev_priv->regs + reg + 0x180000);         \
        } else {                                                        \