pinctrl: sh-pfc: r8a77965: Add support for INTC-EX IRQ pins

Most pins on the R8A77965 SoC can be configured in GPIO mode for
interrupt and GPIO functionality, while a couple of them can also
be routed to the INTC-EX hardware block (formerly known as IRQC).

On R8A77965 the INTC-EX hardware handles pins IRQ0 -> IRQ5 and
this patch adds support for them to the PFC driver as "intc_ex_irqN".

Based on a similar patch for the R8A7795 PFC driver by Magnus Damm
<damm+renesas@opensource.se>.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
index acd57d5b2fb18b25aa2bbd0e592b74cba2173df8..363ccc3b1bdc7a88974b9e2441dc0dda70c43def 100644 (file)
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
@@ -1661,6 +1661,51 @@ static const unsigned int avb_avtp_capture_b_pins[] = {
 static const unsigned int avb_avtp_capture_b_mux[] = {
        AVB_AVTP_CAPTURE_B_MARK,
 };
+
+/* - INTC-EX ---------------------------------------------------------------- */
+static const unsigned int intc_ex_irq0_pins[] = {
+       /* IRQ0 */
+       RCAR_GP_PIN(2, 0),
+};
+static const unsigned int intc_ex_irq0_mux[] = {
+       IRQ0_MARK,
+};
+static const unsigned int intc_ex_irq1_pins[] = {
+       /* IRQ1 */
+       RCAR_GP_PIN(2, 1),
+};
+static const unsigned int intc_ex_irq1_mux[] = {
+       IRQ1_MARK,
+};
+static const unsigned int intc_ex_irq2_pins[] = {
+       /* IRQ2 */
+       RCAR_GP_PIN(2, 2),
+};
+static const unsigned int intc_ex_irq2_mux[] = {
+       IRQ2_MARK,
+};
+static const unsigned int intc_ex_irq3_pins[] = {
+       /* IRQ3 */
+       RCAR_GP_PIN(2, 3),
+};
+static const unsigned int intc_ex_irq3_mux[] = {
+       IRQ3_MARK,
+};
+static const unsigned int intc_ex_irq4_pins[] = {
+       /* IRQ4 */
+       RCAR_GP_PIN(2, 4),
+};
+static const unsigned int intc_ex_irq4_mux[] = {
+       IRQ4_MARK,
+};
+static const unsigned int intc_ex_irq5_pins[] = {
+       /* IRQ5 */
+       RCAR_GP_PIN(2, 5),
+};
+static const unsigned int intc_ex_irq5_mux[] = {
+       IRQ5_MARK,
+};
+
 /* - SCIF0 ------------------------------------------------------------------ */
 static const unsigned int scif0_data_pins[] = {
        /* RX, TX */
@@ -1883,6 +1928,12 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
        SH_PFC_PIN_GROUP(avb_avtp_capture_a),
        SH_PFC_PIN_GROUP(avb_avtp_match_b),
        SH_PFC_PIN_GROUP(avb_avtp_capture_b),
+       SH_PFC_PIN_GROUP(intc_ex_irq0),
+       SH_PFC_PIN_GROUP(intc_ex_irq1),
+       SH_PFC_PIN_GROUP(intc_ex_irq2),
+       SH_PFC_PIN_GROUP(intc_ex_irq3),
+       SH_PFC_PIN_GROUP(intc_ex_irq4),
+       SH_PFC_PIN_GROUP(intc_ex_irq5),
        SH_PFC_PIN_GROUP(scif0_data),
        SH_PFC_PIN_GROUP(scif0_clk),
        SH_PFC_PIN_GROUP(scif0_ctrl),
@@ -1927,6 +1978,15 @@ static const char * const avb_groups[] = {
        "avb_avtp_capture_b",
 };
 
+static const char * const intc_ex_groups[] = {
+       "intc_ex_irq0",
+       "intc_ex_irq1",
+       "intc_ex_irq2",
+       "intc_ex_irq3",
+       "intc_ex_irq4",
+       "intc_ex_irq5",
+};
+
 static const char * const scif0_groups[] = {
        "scif0_data",
        "scif0_clk",
@@ -1978,6 +2038,7 @@ static const char * const scif_clk_groups[] = {
 
 static const struct sh_pfc_function pinmux_functions[] = {
        SH_PFC_FUNCTION(avb),
+       SH_PFC_FUNCTION(intc_ex),
        SH_PFC_FUNCTION(scif0),
        SH_PFC_FUNCTION(scif1),
        SH_PFC_FUNCTION(scif2),