drm/i915/adl_p: Implement Wa_22011091694

Adding a new hook to ADL-P just to avoid another platform check in
gen12lp_init_clock_gating() but also open to it.

BSpec: 54369
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210514153711.2359617-18-matthew.d.roper@intel.com

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 349cf953c689e40c8316fe44e709a071154dcfbf..07cca3b423bcd6d632d9db05f1d1b6edfe60a4c7 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4170,6 +4170,9 @@ enum {
 #define GEN9_CLKGATE_DIS_4             _MMIO(0x4653C)
 #define   BXT_GMBUS_GATING_DIS         (1 << 14)
 
+#define GEN9_CLKGATE_DIS_5             _MMIO(0x46540)
+#define   DPCE_GATING_DIS              REG_BIT(17)
+
 #define _CLKGATE_DIS_PSL_A             0x46520
 #define _CLKGATE_DIS_PSL_B             0x46524
 #define _CLKGATE_DIS_PSL_C             0x46528

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ef2d1fa60f043ce581b853063785ee84165654bc..32f7806ea12ca97a707c6b46c464b6e4af7d3475 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7141,6 +7141,14 @@ static void gen12lp_init_clock_gating(struct drm_i915_private *dev_priv)
                                 CLKREQ_POLICY_MEM_UP_OVRD, 0);
 }
 
+static void adlp_init_clock_gating(struct drm_i915_private *dev_priv)
+{
+       gen12lp_init_clock_gating(dev_priv);
+
+       /* Wa_22011091694:adlp */
+       intel_de_rmw(dev_priv, GEN9_CLKGATE_DIS_5, 0, DPCE_GATING_DIS);
+}
+
 static void dg1_init_clock_gating(struct drm_i915_private *dev_priv)
 {
        gen12lp_init_clock_gating(dev_priv);
@@ -7618,7 +7626,9 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
  */
 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
 {
-       if (IS_DG1(dev_priv))
+       if (IS_ALDERLAKE_P(dev_priv))
+               dev_priv->display.init_clock_gating = adlp_init_clock_gating;
+       else if (IS_DG1(dev_priv))
                dev_priv->display.init_clock_gating = dg1_init_clock_gating;
        else if (IS_GEN(dev_priv, 12))
                dev_priv->display.init_clock_gating = gen12lp_init_clock_gating;