#define GHWCFG4_NUM_DEV_MODE_CTRL_EP_SHIFT     16
 #define GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK       (0x3 << 14)
 #define GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT      14
-#define GHWCFG4_ACG_SUPPORTED                  BIT(12)
-#define GHWCFG4_IPG_ISOC_SUPPORTED             BIT(11)
-#define GHWCFG4_SERVICE_INTERVAL_SUPPORTED      BIT(10)
 #define GHWCFG4_UTMI_PHY_DATA_WIDTH_8          0
 #define GHWCFG4_UTMI_PHY_DATA_WIDTH_16         1
 #define GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16    2
+#define GHWCFG4_ACG_SUPPORTED                  BIT(12)
+#define GHWCFG4_IPG_ISOC_SUPPORTED             BIT(11)
+#define GHWCFG4_SERVICE_INTERVAL_SUPPORTED      BIT(10)
 #define GHWCFG4_XHIBER                         BIT(7)
 #define GHWCFG4_HIBER                          BIT(6)
 #define GHWCFG4_MIN_AHB_FREQ                   BIT(5)