}
                adev->ip_blocks[i].status.sw = true;
 
-               /* need to do gmc hw init early so we can allocate gpu mem */
-               if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
+               if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON) {
+                       /* need to do common hw init early so everything is set up for gmc */
+                       r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
+                       if (r) {
+                               DRM_ERROR("hw_init %d failed %d\n", i, r);
+                               goto init_failed;
+                       }
+                       adev->ip_blocks[i].status.hw = true;
+               } else if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
+                       /* need to do gmc hw init early so we can allocate gpu mem */
                        /* Try to reserve bad pages early */
                        if (amdgpu_sriov_vf(adev))
                                amdgpu_virt_exchange_data(adev);
        int i, r;
 
        static enum amd_ip_block_type ip_order[] = {
-               AMD_IP_BLOCK_TYPE_GMC,
                AMD_IP_BLOCK_TYPE_COMMON,
+               AMD_IP_BLOCK_TYPE_GMC,
                AMD_IP_BLOCK_TYPE_PSP,
                AMD_IP_BLOCK_TYPE_IH,
        };