if (modifier_has_dcc(modifier) && !force_disable_dcc) {
                uint64_t dcc_address = afb->address + afb->base.offsets[1];
                bool independent_64b_blks = AMD_FMT_MOD_GET(DCC_INDEPENDENT_64B, modifier);
+               bool independent_128b_blks = AMD_FMT_MOD_GET(DCC_INDEPENDENT_128B, modifier);
 
                dcc->enable = 1;
                dcc->meta_pitch = afb->base.pitches[1];
                dcc->independent_64b_blks = independent_64b_blks;
-               if (independent_64b_blks)
-                       dcc->dcc_ind_blk = hubp_ind_block_64b;
-               else
-                       dcc->dcc_ind_blk = hubp_ind_block_unconstrained;
+               if (AMD_FMT_MOD_GET(TILE_VERSION, modifier) == AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) {
+                       if (independent_64b_blks && independent_128b_blks)
+                               dcc->dcc_ind_blk = hubp_ind_block_64b;
+                       else if (independent_128b_blks)
+                               dcc->dcc_ind_blk = hubp_ind_block_128b;
+                       else if (independent_64b_blks && !independent_128b_blks)
+                               dcc->dcc_ind_blk = hubp_ind_block_64b_no_128bcl;
+                       else
+                               dcc->dcc_ind_blk = hubp_ind_block_unconstrained;
+               } else {
+                       if (independent_64b_blks)
+                               dcc->dcc_ind_blk = hubp_ind_block_64b;
+                       else
+                               dcc->dcc_ind_blk = hubp_ind_block_unconstrained;
+               }
 
                address->grph.meta_addr.low_part = lower_32_bits(dcc_address);
                address->grph.meta_addr.high_part = upper_32_bits(dcc_address);