drm/amdgpu: select compute ME engines dynamically

GFX ME right now is one but this could change in
future SOC's. Use no of ME for GFX as start point
for ME for compute for GFX11.

Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index 4f57cf3dac4844450ba8ea86d08ae6d62beddb56..dcef399074492dd9d8f676be21438c92ecbae7cf 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -6456,7 +6456,7 @@ static void gfx_v11_ip_dump(void *handle)
                for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {
                        for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) {
                                /* ME0 is for GFX so start from 1 for CP */
-                               soc21_grbm_select(adev, 1+i, j, k, 0);
+                               soc21_grbm_select(adev, adev->gfx.me.num_me + i, j, k, 0);
                                for (reg = 0; reg < reg_count; reg++) {
                                        adev->gfx.ip_dump_compute_queues[index + reg] =
                                                RREG32(SOC15_REG_ENTRY_OFFSET(