{
        struct sk_buff *skb;
        struct p54_txcancel *cancel;
+       u32 _req_id = le32_to_cpu(req_id);
 
-       if (unlikely(req_id < priv->rx_start || req_id > priv->rx_end))
+       if (unlikely(_req_id < priv->rx_start || _req_id > priv->rx_end))
                return -EINVAL;
 
        skb = p54_alloc_skb(priv, P54_HDR_FLAG_CONTROL_OPSET, sizeof(*cancel),
 
        { SPI_ADRS_DMA_WRITE_BASE,      32, "DMA_RD_BASE " }
 };
 
-static int p54spi_wait_bit(struct p54s_priv *priv, u16 reg, __le32 bits)
+static int p54spi_wait_bit(struct p54s_priv *priv, u16 reg, u32 bits)
 {
        int i;
 
        for (i = 0; i < 2000; i++) {
-               __le32 buffer = p54spi_read32(priv, reg);
+               u32 buffer = p54spi_read32(priv, reg);
                if ((buffer & bits) == bits)
                        return 1;
        }
 static int p54spi_spi_write_dma(struct p54s_priv *priv, __le32 base,
                                const void *buf, size_t len)
 {
-       if (!p54spi_wait_bit(priv, SPI_ADRS_DMA_WRITE_CTRL,
-                            cpu_to_le32(HOST_ALLOWED))) {
+       if (!p54spi_wait_bit(priv, SPI_ADRS_DMA_WRITE_CTRL, HOST_ALLOWED)) {
                dev_err(&priv->spi->dev, "spi_write_dma not allowed "
                        "to DMA write.\n");
                return -EAGAIN;
 
        /* And wait for the READY interrupt */
        if (!p54spi_wait_bit(priv, SPI_ADRS_HOST_INTERRUPTS,
-                            cpu_to_le32(SPI_HOST_INT_READY))) {
+                            SPI_HOST_INT_READY)) {
                dev_err(&priv->spi->dev, "INT_READY timeout\n");
                return -EBUSY;
        }
                goto out;
 
        if (!p54spi_wait_bit(priv, SPI_ADRS_HOST_INTERRUPTS,
-                            cpu_to_le32(SPI_HOST_INT_WR_READY))) {
+                            SPI_HOST_INT_WR_READY)) {
                dev_err(&priv->spi->dev, "WR_READY timeout\n");
                ret = -EAGAIN;
                goto out;