drm/vc4: Fix setting of vertical timings in the CRTC.

It looks like when I went to add the interlaced bits, I just took the
existing PV_VERT* block and indented it, instead of copy and pasting
it first.  Without this, changing resolution never worked.

Signed-off-by: Eric Anholt <eric@anholt.net>

diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c
index 5e84be2e97d01f116065fe4efc56e18702fdc122..93d53c278486eee903926177828af1e3ad3ef211 100644 (file)
--- a/drivers/gpu/drm/vc4/vc4_crtc.c
+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
@@ -212,6 +212,16 @@ static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc)
                                 PV_HORZB_HFP) |
                   VC4_SET_FIELD(mode->hdisplay, PV_HORZB_HACTIVE));
 
+       CRTC_WRITE(PV_VERTA,
+                  VC4_SET_FIELD(mode->vtotal - mode->vsync_end,
+                                PV_VERTA_VBP) |
+                  VC4_SET_FIELD(mode->vsync_end - mode->vsync_start,
+                                PV_VERTA_VSYNC));
+       CRTC_WRITE(PV_VERTB,
+                  VC4_SET_FIELD(mode->vsync_start - mode->vdisplay,
+                                PV_VERTB_VFP) |
+                  VC4_SET_FIELD(vactive, PV_VERTB_VACTIVE));
+
        if (interlace) {
                CRTC_WRITE(PV_VERTA_EVEN,
                           VC4_SET_FIELD(mode->vtotal - mode->vsync_end - 1,