wifi: rtw89: 8852c: disable PCI PHY EQ to improve compatibility

For adaption EQ circuit, this HW design and affected by EIEOS (Electrical
Idle Exit Order Set) amplitude from platform and process from IC, so
disable EQ to improve that.

Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Link: https://msgid.link/20240329015251.22762-5-pkshih@realtek.com

diff --git a/drivers/net/wireless/realtek/rtw89/pci.c b/drivers/net/wireless/realtek/rtw89/pci.c
index 46e24b3d807f2dd4c0e8d291e7bd8f13c102cb1d..c734f6702546a6cb055998d92d71c98ffaf1dba3 100644 (file)
--- a/drivers/net/wireless/realtek/rtw89/pci.c
+++ b/drivers/net/wireless/realtek/rtw89/pci.c
@@ -19,6 +19,31 @@ MODULE_PARM_DESC(disable_clkreq, "Set Y to disable PCI clkreq support");
 MODULE_PARM_DESC(disable_aspm_l1, "Set Y to disable PCI ASPM L1 support");
 MODULE_PARM_DESC(disable_aspm_l1ss, "Set Y to disable PCI L1SS support");
 
+static int rtw89_pci_get_phy_offset_by_link_speed(struct rtw89_dev *rtwdev,
+                                                 u32 *phy_offset)
+{
+       struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
+       struct pci_dev *pdev = rtwpci->pdev;
+       u32 val;
+       int ret;
+
+       ret = pci_read_config_dword(pdev, RTW89_PCIE_L1_STS_V1, &val);
+       if (ret)
+               return ret;
+
+       val = u32_get_bits(val, RTW89_BCFG_LINK_SPEED_MASK);
+       if (val == RTW89_PCIE_GEN1_SPEED) {
+               *phy_offset = R_RAC_DIRECT_OFFSET_G1;
+       } else if (val == RTW89_PCIE_GEN2_SPEED) {
+               *phy_offset = R_RAC_DIRECT_OFFSET_G2;
+       } else {
+               rtw89_warn(rtwdev, "Unknown PCI link speed %d\n", val);
+               return -EFAULT;
+       }
+
+       return 0;
+}
+
 static int rtw89_pci_rst_bdram_ax(struct rtw89_dev *rtwdev)
 {
        u32 val;
@@ -2298,6 +2323,52 @@ static int rtw89_pci_deglitch_setting(struct rtw89_dev *rtwdev)
        return 0;
 }
 
+static void rtw89_pci_disable_eq(struct rtw89_dev *rtwdev)
+{
+       u16 g1_oobs, g2_oobs;
+       u32 backup_aspm;
+       u32 phy_offset;
+       u16 oobs_val;
+       u16 val16;
+       int ret;
+
+       if (rtwdev->chip->chip_id != RTL8852C)
+               return;
+
+       backup_aspm = rtw89_read32(rtwdev, R_AX_PCIE_MIX_CFG_V1);
+       rtw89_write32_clr(rtwdev, R_AX_PCIE_MIX_CFG_V1, B_AX_ASPM_CTRL_MASK);
+
+       g1_oobs = rtw89_read16_mask(rtwdev, R_RAC_DIRECT_OFFSET_G1 +
+                                           RAC_ANA09 * RAC_MULT, BAC_OOBS_SEL);
+       g2_oobs = rtw89_read16_mask(rtwdev, R_RAC_DIRECT_OFFSET_G2 +
+                                           RAC_ANA09 * RAC_MULT, BAC_OOBS_SEL);
+       if (g1_oobs && g2_oobs)
+               goto out;
+
+       ret = rtw89_pci_get_phy_offset_by_link_speed(rtwdev, &phy_offset);
+       if (ret)
+               goto out;
+
+       rtw89_write16_set(rtwdev, phy_offset + RAC_ANA0D * RAC_MULT, BAC_RX_TEST_EN);
+       rtw89_write16(rtwdev, phy_offset + RAC_ANA10 * RAC_MULT, ADDR_SEL_PINOUT_DIS_VAL);
+       rtw89_write16_set(rtwdev, phy_offset + RAC_ANA19 * RAC_MULT, B_PCIE_BIT_RD_SEL);
+
+       val16 = rtw89_read16_mask(rtwdev, phy_offset + RAC_ANA1F * RAC_MULT,
+                                 OOBS_LEVEL_MASK);
+       oobs_val = u16_encode_bits(val16, OOBS_SEN_MASK);
+
+       rtw89_write16(rtwdev, R_RAC_DIRECT_OFFSET_G1 + RAC_ANA03 * RAC_MULT, oobs_val);
+       rtw89_write16_set(rtwdev, R_RAC_DIRECT_OFFSET_G1 + RAC_ANA09 * RAC_MULT,
+                         BAC_OOBS_SEL);
+
+       rtw89_write16(rtwdev, R_RAC_DIRECT_OFFSET_G2 + RAC_ANA03 * RAC_MULT, oobs_val);
+       rtw89_write16_set(rtwdev, R_RAC_DIRECT_OFFSET_G2 + RAC_ANA09 * RAC_MULT,
+                         BAC_OOBS_SEL);
+
+out:
+       rtw89_write32(rtwdev, R_AX_PCIE_MIX_CFG_V1, backup_aspm);
+}
+
 static void rtw89_pci_ber(struct rtw89_dev *rtwdev)
 {
        u32 phy_offset;
@@ -2711,6 +2782,7 @@ static int rtw89_pci_ops_mac_pre_init_ax(struct rtw89_dev *rtwdev)
        const struct rtw89_pci_info *info = rtwdev->pci_info;
        int ret;
 
+       rtw89_pci_disable_eq(rtwdev);
        rtw89_pci_ber(rtwdev);
        rtw89_pci_rxdma_prefth(rtwdev);
        rtw89_pci_l1off_pwroff(rtwdev);

diff --git a/drivers/net/wireless/realtek/rtw89/pci.h b/drivers/net/wireless/realtek/rtw89/pci.h
index 87e7081664c1f4b8bec5168dfef5cc0b603acb71..7666753ae98327175b926afbad3cb81b9dab230b 100644 (file)
--- a/drivers/net/wireless/realtek/rtw89/pci.h
+++ b/drivers/net/wireless/realtek/rtw89/pci.h
@@ -12,11 +12,18 @@
 #define MDIO_PG0_G2 2
 #define MDIO_PG1_G2 3
 #define RAC_CTRL_PPR                   0x00
+#define RAC_ANA03                      0x03
+#define OOBS_SEN_MASK                  GENMASK(5, 1)
+#define RAC_ANA09                      0x09
+#define BAC_OOBS_SEL                   BIT(4)
 #define RAC_ANA0A                      0x0A
 #define B_BAC_EQ_SEL                   BIT(5)
 #define RAC_ANA0C                      0x0C
 #define B_PCIE_BIT_PSAVE               BIT(15)
+#define RAC_ANA0D                      0x0D
+#define BAC_RX_TEST_EN                 BIT(6)
 #define RAC_ANA10                      0x10
+#define ADDR_SEL_PINOUT_DIS_VAL                0x3C4
 #define B_PCIE_BIT_PINOUT_DIS          BIT(3)
 #define RAC_REG_REV2                   0x1B
 #define BAC_CMU_EN_DLY_MASK            GENMASK(15, 12)
@@ -30,6 +37,7 @@
 #define RAC_ANA1E_G1_VAL               0x66EA
 #define RAC_ANA1E_G2_VAL               0x6EEA
 #define RAC_ANA1F                      0x1F
+#define OOBS_LEVEL_MASK                        GENMASK(12, 8)
 #define RAC_ANA24                      0x24
 #define B_AX_DEGLITCH                  GENMASK(11, 8)
 #define RAC_ANA26                      0x26