return r;
        }
 
+       if (adev->vcn.indirect_sram) {
+               r = amdgpu_bo_create_kernel(adev, 64 * 2 * 4, PAGE_SIZE,
+                           AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.dpg_sram_bo,
+                           &adev->vcn.dpg_sram_gpu_addr, &adev->vcn.dpg_sram_cpu_addr);
+               if (r) {
+                       dev_err(adev->dev, "(%d) failed to allocate DPG bo\n", r);
+                       return r;
+               }
+       }
+
        return 0;
 }
 
 
        kvfree(adev->vcn.saved_bo);
 
+       if (adev->vcn.indirect_sram) {
+               amdgpu_bo_free_kernel(&adev->vcn.dpg_sram_bo,
+                             &adev->vcn.dpg_sram_gpu_addr,
+                             (void **)&adev->vcn.dpg_sram_cpu_addr);
+       }
+
        amdgpu_bo_free_kernel(&adev->vcn.vcpu_bo,
                              &adev->vcn.gpu_addr,
                              (void **)&adev->vcn.cpu_addr);
 
        struct amdgpu_vcn_reg   internal, external;
        int (*pause_dpg_mode)(struct amdgpu_device *adev,
                struct dpg_pause_state *new_state);
+
+       bool                    indirect_sram;
+       struct amdgpu_bo        *dpg_sram_bo;
+       void                    *dpg_sram_cpu_addr;
+       uint64_t                dpg_sram_gpu_addr;
+       uint32_t                *dpg_sram_curr_addr;
 };
 
 int amdgpu_vcn_sw_init(struct amdgpu_device *adev);