drm/nv108/fifo: initial support

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

diff --git a/drivers/gpu/drm/nouveau/Makefile b/drivers/gpu/drm/nouveau/Makefile
index b3fa1ba191b7115be412894936c3633bf9221188..a8804254bb31cd0f42d0749e326b915369ceb569 100644 (file)
--- a/drivers/gpu/drm/nouveau/Makefile
+++ b/drivers/gpu/drm/nouveau/Makefile
@@ -232,6 +232,7 @@ nouveau-y += core/engine/fifo/nv50.o
 nouveau-y += core/engine/fifo/nv84.o
 nouveau-y += core/engine/fifo/nvc0.o
 nouveau-y += core/engine/fifo/nve0.o
+nouveau-y += core/engine/fifo/nv108.o
 nouveau-y += core/engine/graph/ctxnv40.o
 nouveau-y += core/engine/graph/ctxnv50.o
 nouveau-y += core/engine/graph/ctxnvc0.o

diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nve0.c b/drivers/gpu/drm/nouveau/core/engine/device/nve0.c
index 3900104976fc7bfc2ca3df441318254bdae3bf97..0fc93472f02fa23b2092e3357634e8ed769dc23d 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/device/nve0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/device/nve0.c
@@ -212,8 +212,8 @@ nve0_identify(struct nouveau_device *device)
                device->oclass[NVDEV_SUBDEV_PWR    ] = &nv108_pwr_oclass;
                device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
                device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
+               device->oclass[NVDEV_ENGINE_FIFO   ] =  nv108_fifo_oclass;
 #if 0
-               device->oclass[NVDEV_ENGINE_FIFO   ] =  nve0_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_software_oclass;
                device->oclass[NVDEV_ENGINE_GR     ] =  nvf0_graph_oclass;
 #endif

diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv108.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv108.c
new file mode 100644 (file)
index 0000000..09362a5
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nv108.c
@@ -0,0 +1,37 @@
+/*
+ * Copyright 2013 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs
+ */
+
+#include "nve0.h"
+
+struct nouveau_oclass *
+nv108_fifo_oclass = &(struct nve0_fifo_impl) {
+       .base.handle = NV_ENGINE(FIFO, 0x08),
+       .base.ofuncs = &(struct nouveau_ofuncs) {
+               .ctor = nve0_fifo_ctor,
+               .dtor = nve0_fifo_dtor,
+               .init = nve0_fifo_init,
+               .fini = _nouveau_fifo_fini,
+       },
+       .channels = 1024,
+}.base;

diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c
index 04f412922d2d43f5a5fbce11185fc2f9f4196e7e..4af3f406896b989cf78470bb2a3bf12b4b594cd2 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c
@@ -36,7 +36,8 @@
 #include <subdev/vm.h>
 
 #include <engine/dmaobj.h>
-#include <engine/fifo.h>
+
+#include "nve0.h"
 
 #define _(a,b) { (a), ((1ULL << (a)) | (b)) }
 static const struct {
@@ -575,15 +576,64 @@ nve0_fifo_uevent_disable(struct nouveau_event *event, int index)
        nv_mask(priv, 0x002140, 0x80000000, 0x00000000);
 }
 
-static int
+int
+nve0_fifo_init(struct nouveau_object *object)
+{
+       struct nve0_fifo_priv *priv = (void *)object;
+       int ret, i;
+
+       ret = nouveau_fifo_init(&priv->base);
+       if (ret)
+               return ret;
+
+       /* enable all available PSUBFIFOs */
+       nv_wr32(priv, 0x000204, 0xffffffff);
+       priv->spoon_nr = hweight32(nv_rd32(priv, 0x000204));
+       nv_debug(priv, "%d subfifo(s)\n", priv->spoon_nr);
+
+       /* PSUBFIFO[n] */
+       for (i = 0; i < priv->spoon_nr; i++) {
+               nv_mask(priv, 0x04013c + (i * 0x2000), 0x10000100, 0x00000000);
+               nv_wr32(priv, 0x040108 + (i * 0x2000), 0xffffffff); /* INTR */
+               nv_wr32(priv, 0x04010c + (i * 0x2000), 0xfffffeff); /* INTREN */
+       }
+
+       nv_wr32(priv, 0x002254, 0x10000000 | priv->user.bar.offset >> 12);
+
+       nv_wr32(priv, 0x002a00, 0xffffffff);
+       nv_wr32(priv, 0x002100, 0xffffffff);
+       nv_wr32(priv, 0x002140, 0x3fffffff);
+       return 0;
+}
+
+void
+nve0_fifo_dtor(struct nouveau_object *object)
+{
+       struct nve0_fifo_priv *priv = (void *)object;
+       int i;
+
+       nouveau_gpuobj_unmap(&priv->user.bar);
+       nouveau_gpuobj_ref(NULL, &priv->user.mem);
+
+       for (i = 0; i < FIFO_ENGINE_NR; i++) {
+               nouveau_gpuobj_ref(NULL, &priv->engine[i].playlist[1]);
+               nouveau_gpuobj_ref(NULL, &priv->engine[i].playlist[0]);
+       }
+
+       nouveau_fifo_destroy(&priv->base);
+}
+
+int
 nve0_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
               struct nouveau_oclass *oclass, void *data, u32 size,
               struct nouveau_object **pobject)
 {
+       struct nve0_fifo_impl *impl = (void *)oclass;
        struct nve0_fifo_priv *priv;
        int ret, i;
 
-       ret = nouveau_fifo_create(parent, engine, oclass, 0, 4095, &priv);
+       ret = nouveau_fifo_create(parent, engine, oclass, 0,
+                                 impl->channels - 1, &priv);
        *pobject = nv_object(priv);
        if (ret)
                return ret;
@@ -621,60 +671,14 @@ nve0_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
        return 0;
 }
 
-static void
-nve0_fifo_dtor(struct nouveau_object *object)
-{
-       struct nve0_fifo_priv *priv = (void *)object;
-       int i;
-
-       nouveau_gpuobj_unmap(&priv->user.bar);
-       nouveau_gpuobj_ref(NULL, &priv->user.mem);
-
-       for (i = 0; i < FIFO_ENGINE_NR; i++) {
-               nouveau_gpuobj_ref(NULL, &priv->engine[i].playlist[1]);
-               nouveau_gpuobj_ref(NULL, &priv->engine[i].playlist[0]);
-       }
-
-       nouveau_fifo_destroy(&priv->base);
-}
-
-static int
-nve0_fifo_init(struct nouveau_object *object)
-{
-       struct nve0_fifo_priv *priv = (void *)object;
-       int ret, i;
-
-       ret = nouveau_fifo_init(&priv->base);
-       if (ret)
-               return ret;
-
-       /* enable all available PSUBFIFOs */
-       nv_wr32(priv, 0x000204, 0xffffffff);
-       priv->spoon_nr = hweight32(nv_rd32(priv, 0x000204));
-       nv_debug(priv, "%d subfifo(s)\n", priv->spoon_nr);
-
-       /* PSUBFIFO[n] */
-       for (i = 0; i < priv->spoon_nr; i++) {
-               nv_mask(priv, 0x04013c + (i * 0x2000), 0x10000100, 0x00000000);
-               nv_wr32(priv, 0x040108 + (i * 0x2000), 0xffffffff); /* INTR */
-               nv_wr32(priv, 0x04010c + (i * 0x2000), 0xfffffeff); /* INTREN */
-       }
-
-       nv_wr32(priv, 0x002254, 0x10000000 | priv->user.bar.offset >> 12);
-
-       nv_wr32(priv, 0x002a00, 0xffffffff);
-       nv_wr32(priv, 0x002100, 0xffffffff);
-       nv_wr32(priv, 0x002140, 0x3fffffff);
-       return 0;
-}
-
 struct nouveau_oclass *
-nve0_fifo_oclass = &(struct nouveau_oclass) {
-       .handle = NV_ENGINE(FIFO, 0xe0),
-       .ofuncs = &(struct nouveau_ofuncs) {
+nve0_fifo_oclass = &(struct nve0_fifo_impl) {
+       .base.handle = NV_ENGINE(FIFO, 0xe0),
+       .base.ofuncs = &(struct nouveau_ofuncs) {
                .ctor = nve0_fifo_ctor,
                .dtor = nve0_fifo_dtor,
                .init = nve0_fifo_init,
                .fini = _nouveau_fifo_fini,
        },
-};
+       .channels = 4096,
+}.base;

diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.h b/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.h
new file mode 100644 (file)
index 0000000..014344e
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.h
@@ -0,0 +1,17 @@
+#ifndef __NVKM_FIFO_NVE0_H__
+#define __NVKM_FIFO_NVE0_H__
+
+#include <engine/fifo.h>
+
+int  nve0_fifo_ctor(struct nouveau_object *, struct nouveau_object *,
+                   struct nouveau_oclass *, void *, u32,
+                   struct nouveau_object **);
+void nve0_fifo_dtor(struct nouveau_object *);
+int  nve0_fifo_init(struct nouveau_object *);
+
+struct nve0_fifo_impl {
+       struct nouveau_oclass base;
+       u32 channels;
+};
+
+#endif

diff --git a/drivers/gpu/drm/nouveau/core/include/engine/fifo.h b/drivers/gpu/drm/nouveau/core/include/engine/fifo.h
index 8c32cf4d83c78bb39773cd11233e59941da52699..26b6b2bb11121e28d4de88f08d4f308ab02fed7a 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/include/engine/fifo.h
+++ b/drivers/gpu/drm/nouveau/core/include/engine/fifo.h
@@ -109,6 +109,7 @@ extern struct nouveau_oclass *nv50_fifo_oclass;
 extern struct nouveau_oclass *nv84_fifo_oclass;
 extern struct nouveau_oclass *nvc0_fifo_oclass;
 extern struct nouveau_oclass *nve0_fifo_oclass;
+extern struct nouveau_oclass *nv108_fifo_oclass;
 
 void nv04_fifo_intr(struct nouveau_subdev *);
 int  nv04_fifo_context_attach(struct nouveau_object *, struct nouveau_object *);