Fixed compiler warnings.

Added missing mappings for PUMA chip.

diff --git a/board/cu824/serial.c b/board/cu824/serial.c
index e33e23e14d9adbbb88195b5a7a6c1baebf761d70..f4ab1a845e866dec3f4682a22c20888f392c020e 100644 (file)
--- a/board/cu824/serial.c
+++ b/board/cu824/serial.c
@@ -25,9 +25,9 @@
 #include "ns16550.h"
 
 #if CONFIG_CONS_INDEX == 1
-static struct NS16550 *console = 0xFE800080;
+static struct NS16550 *console = (struct NS16550 *)0xFE800080;
 #elif CONFIG_CONS_INDEX == 2
-static struct NS16550 *console = 0xFE8000C0;
+static struct NS16550 *console = (struct NS16550 *)0xFE8000C0;
 #else
 #error no valid console defined
 #endif

diff --git a/include/config_pcu_e.h b/include/config_pcu_e.h
index 3d9d8b47bd49451fb38ef0b512d5bbee4ffd0d90..c18c727e182f6fe28b82e06a494f614a3ea871a1 100644 (file)
--- a/include/config_pcu_e.h
+++ b/include/config_pcu_e.h
@@ -385,10 +385,19 @@
 
 /*
  * BR3/OR3: CAN Controller
+ *     BR3: 0x10000401         OR3: 0xffff818a
  */
 #define CAN_CTRLR_BASE         0x10000000      /* CAN Controller */
 #define CAN_CTRLR_OR_AM                0xFFFF8000      /* 32 kB */
-/* ??? */
+#define CAN_CTRLR_TIMING       (OR_BI | OR_SCY_8_CLK | OR_SETA | OR_EHTR)
+
+#if PCU_E_WITH_SWAPPED_CS /* XXX */
+#define CFG_BR4_PRELIM         ((CAN_CTRLR_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
+#define CFG_OR4_PRELIM         (CAN_CTRLR_OR_AM | CAN_CTRLR_TIMING)
+#else /* XXX */
+#define CFG_BR3_PRELIM         ((CAN_CTRLR_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
+#define CFG_OR3_PRELIM         (CAN_CTRLR_OR_AM | CAN_CTRLR_TIMING)
+#endif /* XXX */
 
 /* 
  * BR4/OR4: PUMA Config
@@ -423,22 +432,47 @@
 #endif /* XXX */
 
 /*
- * BR5/OR5: PUMA: SMA Bus 8 Bit
+ * BR6/OR6: PUMA: SMA Bus 8 Bit
+ *     BR6: 0x10200401         OR6: 0xffe00182
  */
 #define PUMA_SMA8_BASE         0x10200000      /* PUMA SMA Bus 8 Bit */
 #define PUMA_SMA8_OR_AM                0xFFE00000      /* 2 MB */
+#define PUMA_SMA8_TIMING       (OR_BI | OR_SCY_8_CLK | OR_EHTR)
+
+#if PCU_E_WITH_SWAPPED_CS /* XXX */
+#define CFG_BR1_PRELIM         ((PUMA_SMA8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
+#define CFG_OR1_PRELIM         (PUMA_SMA8_OR_AM | PUMA_SMA8_TIMING)
+#else /* XXX */
+#define CFG_BR6_PRELIM         ((PUMA_SMA8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
+#define CFG_OR6_PRELIM         (PUMA_SMA8_OR_AM | PUMA_SMA8_TIMING)
+#endif /* XXX */
 
 /*
- * BR6/OR6: PUMA: SMA Bus 16 Bit
+ * BR5/OR5: PUMA: SMA Bus 16 Bit
+ *     BR5: 0x10600801         OR5: 0xffe00182
  */
 #define PUMA_SMA16_BASE                0x10600000      /* PUMA SMA Bus 16 Bit */
 #define PUMA_SMA16_OR_AM       0xFFE00000      /* 2 MB */
+#define PUMA_SMA16_TIMING      (OR_BI | OR_SCY_8_CLK | OR_EHTR)
+
+#if PCU_E_WITH_SWAPPED_CS /* XXX */
+#define CFG_BR2_PRELIM         ((PUMA_SMA16_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
+#define CFG_OR2_PRELIM         (PUMA_SMA16_OR_AM | PUMA_SMA16_TIMING)
+#else /* XXX */
+#define CFG_BR5_PRELIM         ((PUMA_SMA16_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
+#define CFG_OR5_PRELIM         (PUMA_SMA16_OR_AM | PUMA_SMA16_TIMING)
+#endif /* XXX */
 
 /*
  * BR7/OR7: PUMA: external Flash
+ *     BR7: 0x10a00801         OR7: 0xfe000182
  */
 #define PUMA_FLASH_BASE                0x10A00000      /* PUMA external Flash */
 #define PUMA_FLASH_OR_AM       0xFE000000      /* 32 MB */
+#define PUMA_FLASH_TIMING      (OR_BI | OR_SCY_8_CLK | OR_EHTR)
+
+#define CFG_BR7_PRELIM         ((PUMA_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
+#define CFG_OR7_PRELIM         (PUMA_FLASH_OR_AM | PUMA_FLASH_TIMING)
 
 /*
  * Memory Periodic Timer Prescaler