reg |= FIELD_PREP(DWC3_GFLADJ_REFCLK_FLADJ_MASK, fladj)
            |  FIELD_PREP(DWC3_GFLADJ_240MHZDECR, decr >> 1)
            |  FIELD_PREP(DWC3_GFLADJ_240MHZDECR_PLS1, decr & 1);
+
+       if (dwc->gfladj_refclk_lpm_sel)
+               reg |=  DWC3_GFLADJ_REFCLK_LPM_SEL;
+
        dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
 }
 
        else
                reg |= DWC3_GUSB2PHYCFG_ENBLSLPM;
 
-       if (dwc->dis_u2_freeclk_exists_quirk)
+       if (dwc->dis_u2_freeclk_exists_quirk || dwc->gfladj_refclk_lpm_sel)
                reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
 
        dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
                                "snps,dis-tx-ipgap-linecheck-quirk");
        dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev,
                                "snps,parkmode-disable-ss-quirk");
+       dwc->gfladj_refclk_lpm_sel = device_property_read_bool(dev,
+                               "snps,gfladj-refclk-lpm-sel-quirk");
 
        dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
                                "snps,tx_de_emphasis_quirk");
 
 #define DWC3_GFLADJ_30MHZ_SDBND_SEL            BIT(7)
 #define DWC3_GFLADJ_30MHZ_MASK                 0x3f
 #define DWC3_GFLADJ_REFCLK_FLADJ_MASK          GENMASK(21, 8)
+#define DWC3_GFLADJ_REFCLK_LPM_SEL             BIT(23)
 #define DWC3_GFLADJ_240MHZDECR                 GENMASK(30, 24)
 #define DWC3_GFLADJ_240MHZDECR_PLS1            BIT(31)
 
        unsigned                dis_del_phy_power_chg_quirk:1;
        unsigned                dis_tx_ipgap_linecheck_quirk:1;
        unsigned                parkmode_disable_ss_quirk:1;
+       unsigned                gfladj_refclk_lpm_sel:1;
 
        unsigned                tx_de_emphasis_quirk:1;
        unsigned                tx_de_emphasis:2;