clk: zynq: Update the parameters to zynq_clk_register_periph_clk

In case there are only one gate or the two_gate is 0 the clk1 clock
passed is not used. We are passing 0 which is arm_pll.
Pass a invalid clock instead.

Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Link: https://lore.kernel.org/r/20220222130903.17235-3-shubhrajyoti.datta@xilinx.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/drivers/clk/zynq/clkc.c b/drivers/clk/zynq/clkc.c
index 434511dcf5cb240604d0c96b1c62046e1d730dc0..7bdeaff2bfd68b00a25e6cd9ef4f0623a8b2cc9a 100644 (file)
--- a/drivers/clk/zynq/clkc.c
+++ b/drivers/clk/zynq/clkc.c
@@ -355,14 +355,14 @@ static void __init zynq_clk_setup(struct device_node *np)
                                periph_parents, enable);
        }
 
-       zynq_clk_register_periph_clk(lqspi, 0, clk_output_name[lqspi], NULL,
-                       SLCR_LQSPI_CLK_CTRL, periph_parents, 0);
+       zynq_clk_register_periph_clk(lqspi, clk_max, clk_output_name[lqspi], NULL,
+                                    SLCR_LQSPI_CLK_CTRL, periph_parents, 0);
 
-       zynq_clk_register_periph_clk(smc, 0, clk_output_name[smc], NULL,
-                       SLCR_SMC_CLK_CTRL, periph_parents, 0);
+       zynq_clk_register_periph_clk(smc, clk_max, clk_output_name[smc], NULL,
+                                    SLCR_SMC_CLK_CTRL, periph_parents, 0);
 
-       zynq_clk_register_periph_clk(pcap, 0, clk_output_name[pcap], NULL,
-                       SLCR_PCAP_CLK_CTRL, periph_parents, 0);
+       zynq_clk_register_periph_clk(pcap, clk_max, clk_output_name[pcap], NULL,
+                                    SLCR_PCAP_CLK_CTRL, periph_parents, 0);
 
        zynq_clk_register_periph_clk(sdio0, sdio1, clk_output_name[sdio0],
                        clk_output_name[sdio1], SLCR_SDIO_CLK_CTRL,