drm/i915: Set GAC_ECO_BITS register on Gen7+

According to BSpec GAC_ECO_BITS register exists on Gen7 platforms as
well. Configure it accordingly.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index a336c4d609a2d1f4c0650c095cf4d8e77d325e9f..fae638072d7d1bba9f6201110597d60257324d72 100644 (file)
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -117,6 +117,11 @@ static int gen6_ppgtt_enable(struct drm_device *dev)
                                       ECOCHK_PPGTT_CACHE64B);
                I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
        } else if (INTEL_INFO(dev)->gen >= 7) {
+               uint32_t ecobits;
+
+               ecobits = I915_READ(GAC_ECO_BITS);
+               I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
+
                I915_WRITE(GAM_ECOCHK, ECOCHK_PPGTT_CACHE64B);
                /* GFX_MODE is per-ring on gen7+ */
        }